Arteris, Inc. · NASDAQ:AIP
Arteris — Linley Spring Processor Conference 2020
15 slides from Arteris's conference presentation, Apr 9, 2020
Slide 1: Implementing Low Power AI SoCs Using NoC Interconnect Technology
Implementing Low Power AI SoCs Using NoC Interconnect Technology LINLEY SPRING PROCESSOR CONFERENCE 2020 9 APRIL 2020 MATTHEW MANGAN Applications Engineer, Arteris IP [email protected] 2020 Spring Processor Conference April 6 – 9, 2020
Slide 2: The NoC interconnect is the SoC architecture
The NoC interconnect is the SoC architecture Arm® Cortex® CPU Subsystem Safety Island / Safety-Critical Subsystem Machine Learning Subsystem A76AE A76AE A76AE A76AE DCLS CPU Cluster IP IP A76AE A76AE A76AE A76AE FlexNoC Interconnect DSU (L3 cache) DSU (L3 cache) SRAM FLASH IP CHI & ACE Protocols Nco
Slide 3: NoC interconnect design
NoC component Hard IP NoC interconnect design • Complex circuit built of protocol converters, packetizers, switches, adapters. • Fills area between hard IPs • Balance between architectural specs (latency, QoS), power consumption and physical constraints • In NoC creation tools components are multi-v
Slide 4: NoCs are intrinsically low power
NoCs are intrinsically low power • Fewer wires ＝ Fewer gates ＝ Less power, active and leakage • Break communication path in small segments – Power only active segments • Simple internal protocol ＝ Small network elements; aggressive clock gating • Support for very low frequency operation – Fully comb
Slide 5: 3 levels of clock gating
3 levels of clock gating ALLOW NOC IP TO PROVIDE CRITICAL SOC-LEVEL POWER CONTROL Which D flip-flops Level (DFFs)? Enabling Source Count 1. Local Gating Datapath registers Synthesis tools Thousands 2. Unit-Level Gating Control logic registers RTL – Functional combinatorial logic Dozens 3. Root Clock
Slide 6: 1. Local Clock Gating (Datapath Self-Gating)
1. Local Clock Gating (Datapath Self-Gating) • EDA synthesis tools infer enables for groups of DFFs at the register level – Synopsys Power Compiler, Cadence Genus Synthesis Solution • Infers groups of DFFs with identical enables, implementing each group with one clock gate element – Gating cells are
Slide 7: 2. Unit-Level Clock Gating
2. Unit-Level Clock Gating • By default, NoC structural synthesis infers clock gating units from links, network interface units (NIUs), and pseudo-switches I I • Unit Gater IP tracks unit activity Clk Arb Unit • An IP unit that is not processing a packet is Crossbar Gater completely gated and it is
Slide 8: 3. Root Clock Gating
3. Root Clock Gating • A SoC can be split into several power domains that can be independently controlled by the SoC Power NIU NIU NIU NIU NIU Manager Unit SoC Power Manager NIU NIU NIU NIU NIU • Multiple NoC instances can NoC NoC existing in a single power PwrCtl PwrCtl domain, or multiple domains
Slide 9: Gracefully deal with Multiple Domains
Gracefully deal with Multiple Domains Always on I0 I1 I2 • Partitioning inside and outside the NoC NoC NIU NIU • Hardware support for NIU clean state transitions disc disc disc • Handshake communication with ctrlr Power Manager disc disc disc • Wake-up on demand NIU • Error handling ctrlr NIU NIU Ma
Slide 10: Same methods provide IP block isolation for functional safety
Same methods provide IP block isolation for functional safety FROM JOINT PRESENTATION WITH ARM Safety island Arm Ethos- Cortex-R52 N77 NPU Audio Display Mali C71 FAULT Socket power SoC disconnect PMU Safety controller NoC power controller Mem Ctrl SRAM ROM/Flash UART UART 9 April 2020 Copyright © 20
Slide 11: Arteris NoC technology vs. Cascaded Crossbars
Benchmarking (Done by Arteris IP customers) Arteris NoC technology vs. Cascaded Crossbars Interconnect Size NoC Power Chip # (masters x slaves) NoC Performance Consumption NoC Area 1 60x50 Better 3.9x lower 50% smaller (1.2 MGates vs. 2.4 MGates) 2 13x26 Better 1.6x lower 20% smaller 3 14x12 Better
Slide 12: About Toshiba ADAS SoC
About Toshiba ADAS SoC PRODUCTION CHIP WITH AI (DNN) REQUIRING HIGH PERFORMANCE, LOW POWER & SAFETY • Heterogeneous architecture achieves over 20 TOPS and 2 TOPS/W • Power consumption of cache coherent Processing Island is 2.73 W (running SW on evaluation board) Source: Toshiba MPSoC 2019 Source: To
Slide 13: Arteris IP in Toshiba ADAS SoC
Arteris IP in Toshiba ADAS SoC NOC INTERCONNECT IP ENABLES LOW POWER, HIGH PERFORMANCE AND SAFETY PI Domain ( ASIL C ) SI Domain ( ASIL D ) • Cache Coherent Interconnect: Ncore • Non-coherent Interconnect: FlexNoC with Resilience Package Ncore Ncore FlexNoC FlexNoC – 8 NoC instances and all of them
Slide 14: NoC IP is critical to low power AI processing
NoC IP is critical to low power AI processing • Edge AI/ML SoCs have huge TOPS requirements… …and stringent power budgets! • State-of-the-art NoCs manage SoC-level power consumption using 3 levels of clock gating 1. Local/Datapath 2. Unit-Level 3. Root • The most complex Edge AI SoCs (like ADAS) rel
Slide 15: Thank you!
Thank you! [email protected]