Amplitech Group, Inc. · NASDAQ:AMPG

Amplitech — Technical Presentation (November 2018)

12 slides from Amplitech's technical presentation, Nov 29, 2018

  1. Slide 1: A Field Effect Transistor which can be biased to achieve a uniform depletion region

    A Field Effect Transistor which can be biased to achieve a uniform depletion region Presented By Dr Alfred Grayzel November 29, 2018 West Coast Operation: East Coast Operation: 4921 Robert J. Mathews Parkway, Suite 1 7311-F Grove Road El Dorado Hills, CA 95762 USA Frederick, MD 21704 USA Tel: 916-54

  2. Slide 2: Collector current vs voltage for BJT; drain current vs voltage for MOSFET

    SLIDE #1 Figure 1a. Collector current Vs Collector voltage for BJT Figure 1b. Drain current Vs Drain voltage for MOSFET 2 of 12

  3. Slide 3: Class E and Class F Waveforms

    SLIDE #2 Class E Waveform and current Waveforms Figure 2b Class F Waveform Figure 2a 3 of 12

  4. Slide 4: Drain current vs drain voltage when knee voltage is zero

    SLIDE #3 Drain Current Vs Drain voltage for MOSFET when “knee voltage” is zero. 4 of 12

  5. Slide 5: Saturation drain current of JFET and MOSFET

    SLIDE #4 The drain current when a JFET is saturated: Idsat = G0 (Vg – Vp – (2/3)(Vbi – Vp){1 – [(Vbi – Vg)/(Vbi – Vp)]3/2}) (4.1) The drain current when a MOSFET is saturated using square law analysis: Idsat = (Zµ’n C0/2L )(Vg - VT )2 (4.2) 5 of 12

  6. Slide 6: JFET channel under pinchoff conditions

    SLIDE #5 Figure 5a. Figure 5b. The diagrams show the channel of a JFET under different conditions: Figure 5a, the drain voltage equals the pinchoff voltage Figure 5b, the drain voltage exceeds the pinchoff voltage. 6 of 12

  7. Slide 7: Voltage drop along JFET channel; Grayzel JFET

    SLIDE #6 Figure 6a. The voltage drop along the channel for the JFET when a SEVEN-volt battery is connected to the drain terminal and the source terminal is grounded. Figure 6b. A “GRAYZEL JFET” where each section of the gate is biased by means of a separate battery. 7 of 12

  8. Slide 8: Grayzel MOSFET with biased gate sections

    SLIDE #7 Figure 7a. An n-type “GRAYZEL MOSFET”. Figure 7b. An n-type “GRAYZEL MOSFET” where each section of the gate is biased by means of a battery and a resistor network. 8 of 12

  9. Slide 9: Grayzel FET with a square-wave gate voltage

    SLIDE #8 The “GRAYZEL FET” with a square-wave gate voltage. The susceptance of the channel as a function of time. G(t) = .5G0 + g(t) where, g(t) = (2G0/π)( Cosθ -Cos(3θ)/3+ Cos(5θ)/5- Cos(7θ)/7 +…. = (2G0/π)∑∞𝑘𝑘=1(-1) k-1 Cos((2k-1)θ)/ (2k-1) (8.1) The drain voltage as a function of time. Vd(t) =…

  10. Slide 10: Schematic and equivalent circuit of FET amplifier

    SLIDE #9 Figure 9a. A schematic of an FET amplifier Figure 9b. The equivalent circuit of the FET amplifier shown in Figure 9a 10 of 12

  11. Slide 11: Output power and efficiency solution

    SLIDE #10 The “GRAYZEL FET” with a square-wave gate voltage The solution for Id(t) is derived in the appendix to [12] Id(t) = Vd(t)G(t) = [V0 + v(t)][0.5G0 + g(t)] = 0.5V0G0 + V0g(t) + 0.5G0v(t)+v(t)g(t) (10.1) The solution for the output power and efficiency; derived in the appendix [12] P1 = .5(GL

  12. Slide 12: Efficiency vs GL/G0

    SLIDE #11 Efficiency Vs GL/G0 12 of 12

AmpliTech Group — Technical Presentation (November 2018) on 6ix