Arteris, Inc. · NASDAQ:AIP
Arteris — Technical Presentation (August 2023)
15 slides from Arteris's technical presentation, August 2023
Slide 1: Safety Considerations for Network-on-Chip (NoC) Development
Safety Considerations for Network-on-Chip (NoC) Development Update for IQPC ISO 26262 and SOTIF Attendees Stefano Lorenzini, Fellow and Functional Safety Manager • CTO Office Frank Schirrmeister, VP Solutions & Business Development [email protected] August 2023 1 © 2023 Arteris, Inc.
Slide 2: Arteris – A Leading SoC System IP Company
Arteris – A Leading SoC System IP Company ü Silicon-proven IP used in 3 billion+ SoCs shipped to date ü 200+ customers and 700+ SoC design starts to date ü Significant share in the automotive ADAS SoC market ü Strong presence in Artificial Intelligence/Machine Learning (AI/ML) System IP ü Broad supp
Slide 3: Arteris Focus
Arteris Focus NoC Interconnect IP Protocol converters, switches, rate adaptors, etc. Hardware Software NoC Interface IP Interface Additional interconnects & IP blocks connected to NoC IPs SoC Integration Automation SoC IP blocks connected & configured with Arteris IP software 3 © 2023 Arteris, Inc.
Slide 4: The Arteris Ecosystem
The Arteris Ecosystem Automotive Communications Consumer Enterprise & Industrial Electronics Computing Fabless Semiconductors & IDMs Software Synopsys, Cadence, Systems on Chips EDA Siemens Lauterbach, IAR, GreenHills Arteris Magillem (SoC)s Sondrel, Dreamchip, Verisilicon, Andes, Inomize SiFive, Im
Slide 5: Functional Safety
Functional Safety Autonomous vehicles and robots are a huge global opportunity § “Absence of unreasonable risk due to hazards caused by malfunctions” § Systems must function correctly – Products must be properly specified and developed accordingly: Systematic capability – Faults must be detected and
Slide 6: Example System requiring Functional Safety
Example System requiring Functional Safety Safety island CPU Accelerator Graphics Audio Display FAULT Intelligent NoC =? =? =? HW Unit Duplication Safety-critical Safety controller ECC & Parity – Transport NoC Integrated safety controller Initiator Timeout Protocol Validity checker =? =? =? Mem Ctrl
Slide 7: Example NoC Functional Safety Mechanisms
Example NoC Functional Safety Mechanisms Function Failure Modes Safety Mechanisms Packetization External interface corruption; External placeholder (ECC/Parity); Packet External protocol violation; Packet validity checker; Duplication; Initiator timeout corruption Transport Packet corruption ECC/Par
Slide 8: Detecting Errors with FlexNoC: Timeout
Detecting Errors with FlexNoC: Timeout Addresses transient faults § If a component is stuck, timeout allows detection § Implemented for NoC initiators/masters and targets/slaves § NoC counts clock cycles when transactions are pending, and resets at the completion of each response 8 © 2023 Arteris, I
Slide 9: Timeout Setting are Determined Based on FHTI
Timeout Setting are Determined Based on FHTI § Fault handling time interval (FHTI) affects choice of timeout interval – Can be one determinant of Time to Detect Fault – Timeout setting is measured in cycles, usually very small compared to Time to Detect Fault Source: ISO FDIS 26262-1:2018 9 © 2023 A
Slide 10: Isolating IP Blocks with the NoC for Runtime LBIST
Isolating IP Blocks with the NoC for Runtime LBIST § LBIST performed on IP Block (like Arm NPU) during Fault Handling Time Interval (FHTI) § Prerequisite is to isolate IP from rest of NoC prior to start of LBIST § Technical solution: – Isolate IP block plus attached NoC network interface unit (NIU)
Slide 11: Isolate Components for LBIST Using NoC Power Domains
Isolate Components for LBIST Using NoC Power Domains Safety island CPU Accelerator Graphics Audio Display FAULT Socket power Safety controller NoC disconnect SoC power PMU controller Mem Ctrl SRAM ROM/Flash UART UART 11 © 2023 Arteris, Inc.
Slide 12: End-to-End Interface Protection
End-to-End Interface Protection Unique to Arteris NoC IP § Two types of interfaces – AXI interface protection - when available -is natively used by Arteris NoC § Example: Arm Cortex-R52 – “Regular” AXI interfaces § Arteris interconnect allows interoperability between both types – Terminates / rebuil
Slide 13: Interface Protection for All Safety-Critical IP Blocks
Interface Protection for All Safety-Critical IP Blocks • CPU interface protection NIU initiator ECC / Parity • Control checks and/or generation – All command redundancy is generated/terminated – 32/64 bits AXI socket support – ODD/EVEN parity support and ECC transport • Data – Cortex ECC terminated/
Slide 14: FlexNoC Supports Mission Critical SoCs
FlexNoC Supports Mission Critical SoCs Safety island • Functional Safety ISO 26262 documentation & analysis CPU FAULT Accelerator Graphics Audio Display (FMEDA/DFA) =? =? =? • Unit duplication - fault detection Safety-critical • Packet consistency checkers Safety controller NoC • Safety controller •
Slide 15: Thank you
Thank you Arteris, Inc. All rights reserved worldwide. Arteris, Arteris IP, the Arteris IP logo, and the other Arteris marks found at https://www.arteris.com/trademarks are trademarks or registered trademarks of Arteris, Inc. or its subsidiaries. All other trademarks are the property of their respec