Samsung Electronics Co., Ltd. · KRX:005930
Samsung Electronics — Technical Presentation (2018)
20 slides from Samsung Electronics's technical presentation, 2018
Slide 1: System Aware ESD Design
2018 International ESD Workshop System Aware ESD Design System Mindset For A Better Foundry Jordan Davis, Sukjin Kim, Radhakrishnan Sithanandam, Chanhee Jeon, Han-gu Kim Samsung Electronics, Foundry
Slide 2: Biography
Biography Career Started EE Career at ON Semiconductor in March 2008 as design intern ON Semiconductor ESD discrete device & process designer, 2009 - 2017 Samsung Electronics, HQ, Foundry Division, ESD verification, 2017 - present Education B.S.E in electrical engineering in 2009, Arizona St
Slide 3: Abstract
Abstract With the increased complexity of ESD needs and the blurring of the lines between system and IC protection there has become a need for hybrid protection schemes relying on both on-chip and off-chip ESD devices to achieve ESD / EMC requirements. [1] Because of the interaction between syst
Slide 4: Objectives
Objectives Outline the ideal and real world of ESD design and verification Give an overview of how knowing the system can improve the ESD design and verification process at both the system and IC level Review a case study of how testing a customer supplied board can improve the ESD verificatio
Slide 5: System Efficient ESD Design
System Efficient ESD Design A foundry’s place in the SEED approach [2] But where’s the foundry? PCB Design TVS IC Design Design System Design 2018 International ESD Workshop Page 5
Slide 6: The Reality Of ESD Design
The Reality Of ESD Design ESD protection is considered in system design Not as co-design, but as specs to meet Clear understanding and needs are still a mystery to customers Why aren’t PCB Why aren’t your devices your devices Design TVS protecting surviving IC Design Design System Design But st
Slide 7: The Foundry Role in ESD
The Foundry Roll in ESD Perception: Generate PDK / run verification / make suggestions IP The System Reality 2018 International ESD Workshop Page 7
Slide 8: System Requirements ≠ IC Specs
System Requirements ≠ IC Specs Customers often impose system and chip requirements without understanding of actual needs The wrong Reasons The competitor survives more so meet it… Greater the IC survival means greater the system survival… Not know what to design to can be the real problem Hi
Slide 9: System Aware ESD Verification / Design
System Aware ESD Verification / Design When the system can’t be changed… Get more info than just specs Know how much protection is needed Foundry verifies ESD performance on chip Good inputs give info about IC survival and system needs Defined System Design IC ESD Verification System Stress S
Slide 10: A Different Approach To Knowing What's Needed
A Different Approach To Knowing What’s Needed System Aware ESD Verification / Design Concept Customers won’t change, so we need to work smarter! Not just designing IC specs, but system needs Better understanding of transient waveform distortion at IC pads – duration, peak current, etc. System
Slide 11: Vby1 Timing Controller Case
Vby1 Timing Controller Case Timing controller was developed and ESD verification completed When tested in the system there were pin failures Better understand upfront of system needs could have helped prevent need for failure analysis and resulting delays System Requirements IC Specs Pad Syste
Slide 12: Vby1 Timing Controller Case
Vby1 Timing Controller Case Typical ESD verification Bump to Bump resistances, current density Calibrate measured peak current at pad to simulation to find potential weak points in device Additionally, potential victim transistors VDD Bump to bump Clamp Bump to clamp Current density Victim tra
Slide 13: A Better Way
A Better Way Vby1 Timing Controller Example Case Current Path IO Pad to TLP Injection VSS Pad Point (connector pins) Data Data Lines Lines (w/ TVS) (w/o TVS) System test methodology benefits Gives system need for current at IC pads o Realistic input for ESD verification tools Validate effectiven
Slide 14: Measurement Test Setup
Measurement Test Setup Current Probe Connection representing current path through IC Unconnected probe Unconnected probe No IC Current Vss Pin TLP GND Plane Path IO Pins On Board GND TVS Unprotected IO Protected IO TLP Pulse Board Connector 2018 International ESD Workshop Page 14
Slide 15: TLP Current Pulse Comparison
TLP Current Pulse Comparison of TLP Current to Current Through Pad 14 TLP Current Pulse 12 Pad Current w/o TVS 10 Pad Current w/ TVS Current (A) 8 6 4 2 0 0 50 100 150 200 Time (ns) Measurements show actual current through the IC pad with ≈1/3 Ω resistance between IO and Vss 2018 International ESD W
Slide 16: TVS Evaluation
TVS Evaluation PCB TLP Results 16 14 TLP Pulse 12 Current (A) 10 Total Current Total Current 8 Pad Current w/o TVS Measured at Pad 6 Pad Current w/o TVS 4 Pad Current w/ TVS Pad Current w/ TVS 2 0 4 6 8 10 12 Voltage (V) TVS turns on and reduces current at the pad by 9A 2018 International ESD Worksh
Slide 17: Conclusion
Conclusion It was proposed that by measuring the waveform of a transient pulse applied to an electronic system, a system level spec such as IEC 61000-4-2 could be translated to usable input for IC ESD verification. 100ns TLP is well known for it’s correlation factor of ≈ 2A / kV [3] thus making it w
Slide 18: Conclusion
Conclusion Given a know failure point of the IC pins, an estimate of the needed survival level of the IC could be determined for any system and system level protection. This information could also be used to validate the effectiveness of differing TVS devices. By looking at the system that ICs are g
Slide 19: ESD Is No Laughing Matter…
ESD Is No Laughing Matter… [4] 2018 International ESD Workshop Page 19
Slide 20: References
References 1. G. Boselli, A. Salman, J. Brodsky and H. Kunz, "The relevance of long-duration TLP stress on system level ESD design," Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010, Reno, NV, 2010, pp. 1-10. 2. Industry Council White Paper 3 PI Rev1 Dec 2010 3. P. Besse, J.