Renesas Electronics Corporation · TSE:6723
Renesas Electronics — Technical Presentation (October 2023)
12 slides from Renesas Electronics's technical presentation, Oct 10, 2023
Slide 1: Tessent Streaming Scan Network Implementation for Renesas Heterogeneous Multi-Core SoC
Tessent Streaming Scan Network Implementation for Renesas Heterogeneous Multi-Core SoC OCT 10, 2023 Hiroyuki Iwata DFT Platform Technology Section Digital Design Technology Department RENESAS ELECTRONICS CORPORATION © 2023 Renesas Electronics Corporation. All rights reserved.
Slide 2: About Renesas Electronics Corporation
About Renesas Electronics Corporation Our mission is to develop a safer, healthier, greener, and smarter world by providing intelligence to our four focus growth segments: Automotive, Industrial, Infrastructure, and IoT that are all vital to our daily lives, meaning our products and solutions are em
Slide 3: Outline
Outline 1. Challenges of DFT for Heterogeneous SoC 2. SSN Implementation method for Heterogeneous SoC 3. Conclusion © 2023 Renesas Electronics Corporation. All rights reserved. Page 3
Slide 4: Market Trend of Test time
Typical Test Time Expectations Market Trend of Test time 5000% 4000% ▪ Increasing test time with increasing circuit size 3000% ▪ Exponential increase 2000% − Several dozen times in 15 years 1000% − Nearly tripled in the last 4 years 0% 2016 2018 2020 2022 2024 2026 2028 2030 300% ▪ We need to reduce
Slide 5: Legacy Hierarchical DFT Method
Legacy Hierarchical DFT Method ▪ Design Specification of Renesas Previous generation SoC ▪ 50+ hierarchical DFT Cores / coreA 5 ▪ About 210 scan I/O pins (input 160/ output 50) coreB / − Pin-mux structure is used 5 / coreC ▪ Low power process 5 ▪ Test frequency 66 MHz / coreA 3 coreA / coreB MUX 5 c
Slide 6: Latest Renesas SOC Design Specification
Latest Renesas SOC Design Specification ▪ Design Specification Tessent Streaming Scan Network ▪ More than 200 hierarchical DFT Cores / 15 ▪ 200+ scan IO pins (distributed around the chip) CoreA SSH / EDT 15 ▪ Low power process CoreB SSH / EDT 15 ▪ Need to speed up test frequency (target 2x) CoreC SS
Slide 7: Challenges of SSN Implementation
Challenges of SSN Implementation ▪ SSN data bus configuration ▪ Challenges on implementing single SSN data bus ▪ Multiple SSN data bus: less burden on layout for the effective test time reduction 1. Reducing clock skew at IO boundary for faster clock ▪ Single SSN data bus: more effective to test tim
Slide 8: Challenge 1: Reducing clock skew at IO boundary for faster clock
Challenge 1 : Reducing clock skew at IO boundary for faster clock ▪ More than one SSN clock is assigned in accordance with the placement of PAD logic ▪ The clock skew between internal and external clocks is tolerated with SSN FIFO ⇒ The 2x faster clock is expected to be applied by this structure pad
Slide 9: Challenge 2: Wiring from IO to configure large bit-width
Challenge 2 : Wiring from IO to configure large bit-width ▪ Convergence and branch structure allows the large SSN bit-width by exhausting available IOs ▪ The SSN data paths are bundled into one from each PAD logic for input ▪ After passing through all the SSH, the data paths are distributed to each
Slide 10: Challenge 3: Guaranteeing timing between the asynchronous modules
Challenge 3 : Guaranteeing timing between the asynchronous modules ▪ Bus Frequency Divider (BFD) and Bus Frequency multiplier (BFM) are placed between asynchronous modules, e.g. different Power Domains ⇒ The data rate is guaranteed between asynchronous modules PAD SSH FIFO logic PD2 SSH output BFM B
Slide 11: Conclusion
Conclusion ▪ Renesas guarantees high quality testing without compromising test patterns ▪ Tessent SSN is a practical solution for reducing test time and test volume − It can support the complex SoC by utilizing the mechanism that achieves the high-speed operation and facilitates the timing closure −
Slide 12: Renesas.com
Renesas.com © 2023 Renesas Electronics Corporation. All rights reserved.
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