Applied Materials, Inc. · NASDAQ:AMAT
Applied Materials — Investor Day (April 2026)
56 slides from Applied Materials's investor day presentation, Apr 8, 2026
Slide 1: Leading the Future of Logic with Materials-Enabled Scaling
MASTER CLASS April 8, 2026 Leading the Future of Logic with Materials-Enabled Scaling
Slide 2: Forward Looking Statements
Forward Looking Statements This presentation contains forward-looking statements, including those regarding anticipated growth and trends in our businesses and markets, industry outlooks and demand drivers, technology transitions, our business and financial performance and market share positions, ou
Slide 3: Welcome
MASTER CLASS April 8, 2026 Welcome Michael Sullivan Corporate Vice President Head of Investor Relations
Slide 4: Prior View of Semi and WFE Markets
Prior View of Semi and WFE Markets 4 | Applied Materials External
Slide 5: AI Accelerating Semiconductor Demand
AI Accelerating Semiconductor Demand Semiconductor industry revenues can potentially reach $1T this year Source: SIA, Applied Materials 5 | Applied Materials External
Slide 6: WFE Market Outlook
WFE Market Outlook FASTEST GROWING AREAS OF THE MARKET INFLECTIONS Leading-Edge Gate-all-around transistors Foundry/Logic Backside power delivery AP P L I E D M AT E R I AL S 4F2 Process DRAM 3D DRAM Equipment Company in All High-bandwidth memory (HBM) Three Markets Advanced Packaging Hybrid bonding
Slide 7: Inflection-Focused Calendar
Inflection-Focused Calendar APRIL 8 | 9AM PT Logic Master Class Webcast JUNE 25 | 9AM PT DRAM and Advanced Packaging Master Class Webcast OCTOBER 12 Investor Open House at the New EPIC Center Silicon Valley Sunnyvale, CA OCTOBER 13 Investor Breakfast San Francisco, CA | Webcast 7 | Applied Materials
Slide 8: Agenda
AGENDA Mike Sullivan Welcome and Introduction Kevin Moraes, Ph.D. Innovation and Technology Strategy Bala Haran, Ph.D. Logic Transistor Zhebo Chen, Ph.D. Logic Wiring Q&A Kevin, Bala, Zhebo, Mike 8 | Applied Materials External
Slide 9: Innovation and Technology Strategy
MASTER CLASS April 8, 2026 Innovation and Technology Strategy Kevin Moraes, Ph.D. Corporate Vice President Strategy and Marketing Semiconductor Products Group
Slide 10: Inflection-Focused Innovation
Inflection-Focused Innovation Co-Innovate Deliver Working with Valuable new customers to products, chip deliver the most manufacturing valuable solutions processes and from a uniquely AIx services broad portfolio Share Value Create Value To increase As customers ramp margins, R&D more valuable silic
Slide 11: 2025 WFE by Technology – Materials Engineering ~50%
2025 WFE ($115B) by Technology – Materials Engineering ~50% Source: TechInsights, April 2026. Wafer Fab Equipment (WFE) includes front-end fab equipment and excludes “Other WFE” of $4.2 billion. 11 | Applied Materials External
Slide 12: Broad Capabilities Delivered as Unique Connected Solutions
Broad Capabilities Delivered as Unique Connected Solutions Applied Competitors ALD ✓ ✓ ✓ ✓ UNIQUE COMBINATIONS Bonding partner ✓ Cleans partner ✓ ✓ Unit #1 CMP ✓ Process Tools #1 CVD ✓ ✓ ✓ ✓ ✓ ECD ✓ ✓ #1 Epitaxy ✓ ✓ Etch ✓ ✓ ✓ ✓ Co-optimized Solutions Furnace partner ✓ #1 Implant ✓ Lithography partn
Slide 13: Key Levers for Energy Efficient Compute
Key Levers for Energy Efficient Compute Threshold Resistance Capacitance Variability Voltage 13 | Applied Materials External
Slide 14: Logic Transistor
MASTER CLASS April 8, 2026 Logic Transistor Bala Haran, Ph.D. Corporate Vice President Integrated Materials Solutions Semiconductor Products Group
Slide 15: Transistor Evolution and Roadmap
Transistor Evolution and Roadmap N P FinFET GAA Future Architectures FinFET : fin field effect transistor GAA: gate-all-around 15 | Applied Materials External
Slide 16: FinFET → GAA: Improved Performance-Per-Watt
FinFET → GAA: Improved Performance-Per-Watt FinFET GAA FinFET GAA 20% Area Density Stacked Horizontal Channels Vertical Fins Nanosheets 20% Performance Gate Control 3 Sides 4 Sides 30% Power Complexity Moderate High FinFET : fin field effect transistor GAA: gate-all-around 16 | Applied Materials Ext
Slide 17: Logic Gate-All-Around Transistor Formation: High Process Complexity
Logic Gate-All-Around Transistor Formation: High Process Complexity SI CHANNEL In just ~10nm between nanosheet channels >500 steps >5 1-2nm 1Å for GAA transistor distinct per layer precision materials of material required 17 | Applied Materials External
Slide 18: Shallow Trench Isolation (STI) | Integrity
Shallow Trench Isolation (STI) | Integrity Capacitance 2.5% Parasitic Capacitance Sym3 Z Magnum Etch Producer Selectra Etch Producer Precision Selective Nitride PECVD No SiN layer With SiN layer 18 | Applied Materials External
Slide 19: Creating Source/Drain | Etch
Creating Source/Drain | Etch Challenge Tapered Etch Profile Vertical Etch Profile Control Variable Uniform Gate Gate Lengths Lengths Tapered Etch Bottom Flat Etch Bottom Sym3 Z Magnum Etch with Pulsed Voltage Technology 2 19 | Applied Materials External
Slide 20: Creating Source/Drain | Epitaxy
Creating Source/Drain | Epitaxy Challenge Void-Free Uniform Growth • Unique low chamber volume • Tight control over chamber chemistry Uneven cell-to-cell • High-quality films with growth tailored chemistries for different transistors Voids Centura Xtera Epi 20 | Applied Materials External
Slide 21: Creating Source/Drain | Process Co-Optimization with Metrology
Creating Source/Drain | Process Co-Optimization with Metrology PROVision 10 eBeam Metrology Co-optimization for Void-free and Uniform Cell Fill eBeam Side View Source: Applied Materials 40% improvement in cell-to-cell variation High-resolution imaging inside device PROVision 10 eBeam Metrology Centu
Slide 22: Silicon Nanosheet Channel | Surface Treatment
Silicon Nanosheet Channel | Surface Treatment Before Viva After Viva Surface Roughness GAA Transistor Transistor Producer Viva Radical Treatment Speed 22 | Applied Materials External
Slide 23: Gate Stack | High-k Gate Oxide Densification
Gate Stack | High-k Gate Oxide Densification • Decoupled plasma nitride • Post-nitridation anneal (DPN) chamber conformally strengthens nitrogen bonding introduces nitrogen with hafnium oxide Centura DPN HD Treatment 23 | Applied Materials External
Slide 24: Gate Stack | Gate Metals
Gate Stack | Gate Metals 1 2 3 Gate Stack Gate Metals Transistor Behavior Endura Trillium ALD 24 | Applied Materials External
Slide 25: Advanced X-ray Metrology System Endura Trillium ALD
Advanced X-ray Metrology System Endura Trillium ALD 25 | Applied Materials External
Slide 26: Cell Area Reduction Through DTCO
Cell Area Reduction Through DTCO Single Diffusion Break Contact Over Gate Contact Diffusion break Diffusion break Diffusion break Contact 26 | Applied Materials External
Slide 27: Logic Scaling Increasingly Supported with DTCO Innovations
Logic Scaling Increasingly Supported with DTCO Innovations Intrinsic Scaling: Lithography DTCO 1% >25% >40% >50% 16nm 10nm 7nm 5nm 3nm Source: M. Liu/TSMC, ISSCC 2021 27 | Applied Materials External
Slide 28: DTCO Driving Transistor Roadmap
DTCO Driving Transistor Roadmap N P FinFET GAA GAA with GAA with CFET Backside Power Isolation FinFET : fin field effect transistor GAA: gate-all-around CFET: complimentary field effect transistor 28 | Applied Materials External
Slide 29: Logic Wiring
MASTER CLASS April 8, 2026 Logic Wiring Zhebo Chen, Ph.D. Senior Director Metal Deposition Products Semiconductor Products Group
Slide 30: Zooming in on Advanced Chip Wiring
Zooming in on Advanced Chip Wiring >20 layers stacked copper interconnects >2,000 miles wiring Advanced AI chip Source: TechInsights >300 billion transistors Microscope cross section view of chip 3D model of chip 30 | Applied Materials External
Slide 31: Contacts Connect Transistors to Copper Interconnect Wiring
Contacts Connect Transistors to Copper Interconnect Wiring Contacts Interconnect Via contacts Trench contacts Transistor source/drain epitaxy Source: TechInsights Source: TechInsights 31 | Applied Materials External
Slide 32: Contact Liner | Microwave Plasma Deposition
Contact Liner | Microwave Plasma Deposition Conventional Downstream processes erode Microwave Downstream processes have trench bottom when low-density minimal impact on trench bottom Plasma Source Plasma Source contact liners used with new, high-density contact liner Advanced ALD SiN System Contact
Slide 33: Contact Interface | Integrated Etch and Deposition
Contact Interface | Integrated Etch and Deposition Epi Epi Liner Resistance Contact Interface Gate Epi Epi Contact 50% interface Etch Etch Source /drain Non-Integrated Integrated GAA transistor New contact module platform Integrated Materials Solution 50% resistance reduction increases performance*
Slide 34: Contact Metal | Contact Resistance Innovations
Contact Metal | Contact Resistance Innovations Dielectric Via contact Trench Gate contact Source/ drain GAA transistor 34 | Applied Materials External
Slide 35: Contact Metal | Process + Metrology + Digital Tools for Speed
Contact Metal | Process + Metrology + Digital Tools for Speed Spectral Mo ALD Cross-Sectional Opta CMP Cross-Sectional Electrical Testing: TEM~1-2 sites TEM: ~1-2 sites >1,000 sites Overfill Underfill Protrusion Dishing Moly Deposition Moly CMP (Weeks Later) TRADITIONAL LEARNING CYCLE AIX AIX Close
Slide 36: Interconnects Key to Chip Performance and Power
Interconnects Key to Chip Performance and Power Interconnects | Routing of signals and power Power consumption in AI chip: Up to 50% Opportunities: ▪ Minimize power use ▪ Boost operating frequencies ▪ Remove timing bottlenecks Contacts | Connecting transistors to interconnects Transistors | High spe
Slide 37: Copper Interconnect Fabrication
Copper Interconnect Fabrication Dual Damascene Process: Copper Wiring Requires Many Steps New Cu line wiring layer Cu via Cu line CVD dielectric Dielectric etch PVD tantalum PVD tantalum PVD seed ECD copper fill CMP removes surrounds lines forms wiring nitride barrier liner promotes layer supports C
Slide 38: Reducing Wiring Capacitance | Low-k Dielectrics
Reducing Wiring Capacitance | Low-k Dielectrics Challenges Reducing Capacitance with More Porous, Lower-k Dielectrics Wiring Mechanical strength Black Diamond Dielectric Conventional low-k Dielectric constant (k) Maintaining Mechanical Strength of Lower-k Dielectric Films Increased risk of dielectri
Slide 39: Scaling Wiring Increases Resistance
Scaling Wiring Increases Resistance Via resistance (a.u.) >10x Node 10nm 7nm 5nm 3nm line via line a.u.: arbitrary units 39 | Applied Materials External
Slide 40: Reducing Resistance | Selective ALD Barrier
Reducing Resistance | Selective ALD Barrier Challenge Standard barrier integration Copper Reflow Line Via resistance Liner Deposition Via increases Barrier Line up to 100% Materials Modification Treatment from 5nm to 3nm node Integrated On-Board Metrology PVD Selective ALD Deposition ALD CVD Selecti
Slide 41: Reliable Copper Gap Fill | PVD Copper Reflow
Reliable Copper Gap Fill | PVD Copper Reflow Copper Reflow Sequence Repeat cycles First deposition Warm reflow Wafer cool Next deposition Complete Fill with PVD Copper Reflow 41 | Applied Materials External
Slide 42: Innovations to Extend Copper Interconnects
Innovations to Extend Copper Interconnects Endura CuBS RF XT PVD High-coverage barrier & seed Endura Volta Cobalt CVD Seed enhancing cobalt liner & selective metal cap Endura CuBS ALD/PVD ALD barrier Endura Copper Barrier Seed IMS Selective barrier & binary liner 42 | Applied Materials External
Slide 43: Reducing Copper Resistance | Radical and Anneal Treatment
Reducing Copper Resistance | Radical and Anneal Treatment Challenge 2. Enhanced copper grain growth– 1. Radicals are introduced + reducing grain boundaries heat is applied Before Viva After Viva Copper grains Image source: Rogers Corporation Wiring feature at ≥2nm nodes H Metal Layer Hydrogen (H) ra
Slide 44: Reducing Copper Overfill | Chemical Mechanical Planarization
Reducing Copper Overfill | Chemical Mechanical Planarization Challenge Isolated line Dense pattern Target CMP plane Erosion Cu Dishing Cu Oxide Electrochemical Plating Defective CMP Slurry Metrology- controlled In-situ No dishing Pad metrology pressure or erosion conditioner Сatalyst Polisher Wafer
Slide 45: Frontside Wiring Challenges in High-Performance Computing
Frontside Wiring Challenges in High-Performance Computing Wiring congestion Frontside Wiring signal lines & power lines Power voltage drops by up to 50% as layer counts increase Increased capacitance and reliability risks Conventional Frontside Wiring Stack 45 | Applied Materials External
Slide 46: Backside Power Benefits
Backside Power Benefits Frontside Wiring Reduced wiring congestion signal lines Lower wiring resistance and power consumption Backside Wiring 20-30% greater logic density power lines at same lithographic pitch With Backside Power Distribution Network 46 | Applied Materials External
Slide 47: Event Summary and EPIC Preview
MASTER CLASS April 8, 2026 Event Summary and EPIC Preview Kevin Moraes, Ph.D. Corporate Vice President Strategy and Marketing Semiconductor Products Group
Slide 48: Key Messages
KEY AI is driving unprecedented demand for semiconductors and wafer fab equipment MESSAGES Fastest growing areas of the WFE market are leading-edge foundry-logic, DRAM including HBM, and Advanced Packaging, where Applied has strong leadership Materials engineering is increasingly key to roadmap infl
Slide 49: Applied's Technologies at Forefront of Logic Inflections
Applied’s Technologies at Forefront of Logic Inflections Trillium Sym3 Z Magnum Viva ALD Etch Radical Treatment NEW TECHNOLOGIES Precision Selective Nitride Spectral Moly PECVD ALD Endura CuBS PROVision 10 Centura Xtera IMS eBeam Metrology Epitaxy LEADERSHIP TECHNOLOGIES Black Diamond Low-k Centura
Slide 50: Key GAA Steps Enabled by Applied Materials
Key GAA Steps Enabled by Applied Materials Planarizing Wires Creating Epi Opta CMP Nanosheets Centura Prime Epi Creating Contacts Centris Spectral Molybdenum ALD Recessing SiGe Producer Selectra Etch PROVision 10 eBeam Metrology Recessing Si and Removing SiGe Producer Selectra Etch Depositing S/D Ep
Slide 51: Complexity: Innovation to Commercialization Timeline
Complexity: Innovation to Commercialization Timeline UNIVERSITY ENVIRONMENT EQUIPMENT COMPANY CHIPMAKER Commercial Technology Technology Commercial Proof of Equipment & Integrated into Integrated into Chip Idea Concept Process Module Device 5 – 7 YEARS 2 – 3 YEARS 1 – 2 YEARS 1 – 2 YEARS 1 – 2 YEARS
Slide 52: EPIC Will Enable Faster Innovation and Commercialization
EPIC Will Enable Faster Innovation and Commercialization UNIVERSITY ENVIRONMENT EQUIPMENT COMPANY CHIPMAKER Commercial Technology Technology Commercial Proof of Equipment & Integrated into Integrated into Chip Idea Concept Process Module Device 5 – 7 YEARS 2 – 3 YEARS 1 – 2 YEARS 1 – 2 YEARS 1 – 2 Y
Slide 53: All Semiconductor Inflections Going 3D
All Semiconductor Inflections Going 3D Leading-edge Logic DRAM: HBM + Leading Edge System Integration GAA Backside High-Bandwidth Advanced 4F² 3D DRAM Transistor Power Memory Packaging Applied’s materials engineering technologies enable energy-efficient AI 53 | Applied Materials External
Slide 54: Collaborative platform for high-velocity co-innovation and commercialization
Collaborative platform for high-velocity co-innovation and commercialization of next-generation technology 54 | Applied Materials External
Slide 55: Inflection-Focused Calendar
Inflection-Focused Calendar JUNE 25 | 9AM PT DRAM and Advanced Packaging Master Class Webcast OCTOBER 12 Investor Open House at the New EPIC Center Silicon Valley Sunnyvale, CA OCTOBER 13 Investor Breakfast San Francisco, CA | Webcast 55 | Applied Materials External
Slide 56: Applied Materials
APPLIED MATERIALS.. Material Innovation