Synopsys, Inc. · NASDAQ:SNPS

Synopsys — DATE Exhibitor Presentation 2002

24 slides from Synopsys's conference presentation, 2002

1. Slide 1: DATE Exhibitor Presentation 2002

   DATE Exhibitor Presentation 2002 Raul Camposano, CTO, Sr. VP Drawing the Technology Roadmap for EDA in 2002

2. Slide 2: Chip Design

   Chip Design Create Verify System Design Verification Design Logic Implementation Design Integrity Physical © 2001 Synopsys, Inc. (2) CONFIDENTIAL

3. Slide 3: Brings Several Challenges

   Brings Several Challenges Verification Test Timing Closure Design Integrity © 2001 Synopsys, Inc. (3) CONFIDENTIAL

4. Slide 4: Design Implementation

   Design Implementation Test Timing Closure © 2001 Synopsys, Inc. (4) CONFIDENTIAL

5. Slide 5: Interconnect Delay Creates the Timing Closure Problem

   Interconnect Delay Creates the Timing Closure Problem 70 Cu 1.7µΩ-cm Low κ=2.0 60 Line 43µ long .8µ thick Delay (ps) 50 40 30 Interconnect 20 Delay 10 Gate Delay 650 500 350 250 180 150 100 70 ( nm) Technology Node © 2001 Synopsys, Inc. (5) CONFIDENTIAL

6. Slide 6: Capacitive Crosstalk Becomes a First-Order Problem

   Capacitive Crosstalk Becomes a First- Order Problem Worst-case 70 Cu 1.7µΩ-cm Interconnect Low κ=2.0 Delay Due 60 Line 43µ long To X-talk .8µ thick 50 Delay (ps) 40 30 Interconnect 20 Delay 10 650 500 350 250 180 150 100 70 ( nm) Technology Node © 2001 Synopsys, Inc. (6) CONFIDENTIAL

7. Slide 7: The Solution: A New Generation of EDA Tools

   The Solution: A New Generation of EDA Tools Verilog Power/Gr. TLR RTL Chip Planning VHDL Synthesis & DFT Verilog Gates Placement PDEF Placed Gates Chip Assembly Layout Editor Resynthesis CTS Routing GDSII Layout © 2001 Synopsys, Inc. (7) CONFIDENTIAL

8. Slide 8: The Solution: A New Generation of EDA Tools

   The Solution: A New Generation of EDA Tools Verilog Power/Gr. TLR RTL Chip Planning VHDL Synthesis DFT Placement Verilog Placed Gates PDEF Chip Assembly Layout Editor CTS Routing GDSII Layout © 2001 Synopsys, Inc. (8) CONFIDENTIAL

9. Slide 9: The Solution: A New Generation of EDA Tools

   The Solution: A New Generation of EDA Tools Verilog Power/Gr. TLR RTL Chip Planning VHDL Synthesis DFT Placement Routing Chip Assembly Layout Editor GDSII Layout © 2001 Synopsys, Inc. (9) CONFIDENTIAL

10. Slide 10: Design Verification

    Design Verification Verification © 2001 Synopsys, Inc. (10) CONFIDENTIAL

11. Slide 11: Faster, Smarter, and Earlier

    Faster, Smarter, and Earlier Verification System Design & Verification Earlier Simulation Cycles 1T 2007 2x/yr 10B 2001 Faster 100M 1995 Server Farm 1M 10M 100M Testbench Creation Gates Coverage Tools Visualization Tools Verification IP Smarter Timing Verification Formal Verification © 2001 Synopsys

12. Slide 12: VCS 6.1 Highest Performance Simulator

    VCS 6.1 Highest Performance Simulator Schedule Optimization Gate-Level 6.1 Speed-Up Cycle Optimization 6.0.X Hi-level Optimization 5.2 Performance ASIC Sign-Off 5.0 Cycle & 2-State 4.1 Language Optimization 4.0 Native Code 3.X • Up to 3X faster at RTL and gate level Compiled Code 2.0 • 20 - 40% fast

13. Slide 13: 3X Faster for Mixed-HDL

    3X Faster for Mixed-HDL Mixed-HDL Parser Verilog VHDL VCS Scirocco VirSim GUI MX Simulation © 2001 Synopsys, Inc. (13) CONFIDENTIAL

14. Slide 14: Introducing VCS 64-Bit Cross Compile

    Introducing VCS 64-Bit Cross Compile Verilog Verilog Simulation Design Executable VCS 64-bit compile VCS 32-bit simulation on on 64-bit server 32-bit server farm • User compiles on large 64-bit server • Then simulates on 32-bit or 64-bit workstation(s) 64-Bit Workstation Not Required for Simulation!

15. Slide 15: Assertion-Driven Verification

    Assertion-Driven Verification Convergence of HDL Coverage Simulation, Simulation Engines Engines Coverage and Formal Stimulus OpenVera Formal Generation Analysis - plus - Engines Assertions Engines Open Source Standard C++ Verification Integration IP Assertion Language © 2001 Synopsys, Inc. (15) CON

16. Slide 16: CoCentric System Studio: New SystemC Simulator

    CoCentric® System Studio: New SystemC Simulator • SystemC engine sc_assert(request -> status == BUS_OK) • Design entry request -> address address; = request -> data = data; • Debugging • Visualization SystemC • Sim control • Co-simulation • Vera • VCS (Verilog) • Scirocco (VHDL) © 2001 Synopsys, Inc

17. Slide 17: NanoSim: Mixed Signal Simulation

    NanoSim: Mixed Signal Simulation • High performance and capacity ƒ Direct kernel integration of market leading digital and transistor simulators Digital • Ease of use ƒ Importation of analog blocks in digital context ƒ Interactive debug from VCS command interface Analog © 2001 Synopsys, Inc. (17) CO

18. Slide 18: PrimeTime SI: Static Crosstalk Analysis

    PrimeTime® SI: Static Crosstalk Analysis Cross Coupled Capacitance Aggressor CS CW Victim Timing Impact Slow-down Effect Layout shows long parallel run between victim and aggressor net Speed-up Effect Time © 2001 Synopsys, Inc. (18) CONFIDENTIAL

19. Slide 19: Focused Service Offerings

    Focused Service Offerings • World-class tool set ess • Advanced l ri e W methodologies Core • Domain expertise Activities • Compute and infrastructure db oa • Disciplined Br program Context management Activities © 2001 Synopsys, Inc. (19) CONFIDENTIAL

20. Slide 20: What About Avant!?

    What About Avant!? © 2001 Synopsys, Inc. (20) CONFIDENTIAL

21. Slide 21: Synopsys: The Complete Solution

    Synopsys: The Complete Solution System Studio DW VERA Design VCS Compiler Test CM FPGA Formality Prime Physical ArcadiaTime Power CA Nano Star Saber PathM Compiler Sat RM Ext Spice RC Apollo/ Astro DRC Taurus © 2001 Synopsys, Inc. (21) CONFIDENTIAL

22. Slide 22: Single Flow for Tomorrow's Problems

    Single Flow for Tomorrow’s Problems System Studio DW VERA Best VCS Front End Design Compiler Test CM FPGA Formality Prime Physical ArcadiaTime Power CA Nano Star Saber PathM Compiler Sat RM Ext Spice RC Best Apollo/ Back Astro End DRC Taurus © 2001 Synopsys, Inc. (22) CONFIDENTIAL

23. Slide 23: Building Integrated Solutions

    Building Integrated Solutions System Studio System DW VERA Verification Design VCS Compiler Test CM Design FPGA Formality Prime Creation Physical ArcadiaTime Power CA Nano Star Saber PathM CompilerSat RM Ext Spice RC Apollo/ Astro DRC Design Integrity Taurus © 2001 Synopsys, Inc. (23) CONFIDENTIAL

24. Slide 24: Your Design Partner

    SYIOPSYS" Your Design Partner SYNOPSYS"

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