Applied Materials, Inc. · NASDAQ:AMAT
Applied Materials — 2025 SEMICON West Technology Breakfast
90 slides from Applied Materials's conference presentation, Oct 7, 2025
Slide 1: 2025 SEMICON West Technology Breakfast
SS 2025 SEMICON WEST Technology Breakfast ~* @ APPLIED MATERIALS...
Slide 2: Forward Looking Statements
Forward Looking Statements This presentation contains forward-looking statements, including those regarding anticipated growth and trends in our businesses and markets, industry outlooks and demand drivers, technology transitions, our business and financial performance and market positions, our inve
Slide 3: From Atoms to AI
From Atoms to AI Kevin Moraes, Ph.D. Vice President, Semiconductor Products Group OCTOBER 7, 2025 Applied Materials External
Slide 4: Semicon West in Phoenix for the first time
Semicon West in Phoenix for the first time 2025 Applied Materials External
Slide 5: 2024 Tech Breakfast in San Francisco
2024 Tech Breakfast in San Francisco Applied Materials External
Slide 6: Key Takeaways from 2024 Tech Breakfast
Key Takeaways from 2024 Tech Breakfast Applied Materials External
Slide 7: AI's Rapid Evolution
AI’s Rapid Evolution Applied Materials External
Slide 8: Agenda
AGENDA 7:30 Prabu Raja, Ph.D. 8:10 Mukund Srinivasan, Ph.D. Energy-Efficient AI at Scale Enablement 7:40 Jim Chambers, Ph.D. 8:15 Enablement Expert Panel NVIDIA » Bala Haran, Ph.D. Silicon Enablement Accelerated Computing and » Subi Kengeri Package Enablement Semiconductor Ecosystem: » Mike Chudzik,
Slide 9: Energy-Efficient AI at Scale
Energy-Efficient AI at Scale Prabu Raja, Ph.D. President, Semiconductor Products Group OCTOBER 7, 2025 Applied Materials External
Slide 10: AI Intelligent Cloud to Intelligence Everywhere
NOW: FUTURE: AI Intelligent Cloud AI Intelligence Everywhere! Applied Materials External
Slide 11: AI Scaling Faces an Energy Consumption Problem
AI Scaling Faces an Energy Consumption Problem 14% 12% DC Power Consumption % Text 10% AI data centers 8% Language could consume more than 10% of 6% global electricity supply by 2030 4% Visual 2% 0% Traditional Data Center Training Inference Source: Applied Materials Applied Materials External
Slide 12: 10,000x Improvement Needed in Next Years
10,000x Improvement Needed in Next 15 Years 10,000x ENERGY-EFFICIENT PERFORMANCE (1 / femtojoules-picoseconds, log scale) 10,000x PROJECTED 2005 2010 2015 2020 2025 2030 2035 2040 Global Race for AI Leadership Determined by Energy-Efficient Computing Performance Source: Mark Liu and H.-S. Philip Won
Slide 13: Semi Devices Foundational for Energy Efficient Performance
Semi Devices Foundational for Energy Efficient Performance AI AI Leading-edge Logic High-performance DRAM High-bandwidth DRAM Advanced Packaging Power semi (ICAPS) ICAPS: Internet of Things, Communications, Automotive, Power and Sensors Applied Materials External
Slide 14: New 3D Architecture Inflections Offer Big EEP Improvements
New 3D Architecture Inflections Offer Big EEP Improvements AI Leading-edge Logic AI DRAM: HBM + Leading Edge AI Sys. Integration GAA Backside High Bandwidth Vertical Advanced Transistor 3D DRAM Power Memory Transistor Packaging 30% power, 30% density Bandwidth +1,000% EEP +15% EEP +15% 1000x I
Slide 15: Inflection Complexity: Gate-All-Around Transistor Example
Inflection Complexity: Gate-All-Around Transistor Example Copper wiring >15 layers >100km length More Steps More Materials More Interfaces More Step-to- Step Interactions >2,000 >500 PROCESS STEPS FOR GAA TRANSISTOR Applied Materials External
Slide 16: Step-to-Step Interactions Challenges
Clean Contact Module Deposition hardmask Deposition patterning film Track photoresist Lithography trench pattern Lithography contact pattern Etch patterning film open Step-to-Step Etch hardmask open Etch inter-layer dielectric oxide Interactions Ash/etch patterning films Challenges ALD liner deposit
Slide 17: Applied Materials External
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Slide 18: Complexity: Atomic-level Processing at Industrial Scale
Complexity: Atomic-level Processing at Industrial Scale Transistor stack level Die Level Wafer Level Fab Scale Industrial Scale (1Å precision) (mm scale) (300mm) 3 Transistors X ~20B Transistors X ~400 dies / wafer X 100,000 wafers X ~25 fabs per month Giga fab 6 X 1019 with 1Å precision transistors
Slide 19: Advanced Packaging Complexity also Increasing
Advanced Packaging Complexity also Increasing Applied Materials External
Slide 20: Connects Chips in Package
Connects 117 Chips in 1 package >10 Million 3D connections Source: AMD >1.4M Hybrid Bonds >2.9M TSVs >6.0M Bumps Source: AMD, MI300X Processor. Applied Materials analysis Applied Materials External
Slide 21: Packaging Connections Example: Hybrid-Bonding Challenge
Packaging Connections Example: Hybrid-Bonding Challenge Cu Cu dielectric Cu Bond dielectric Cu Failure Cu dielectric NEED: Dielectric-to-dielectric and copper-to-copper bonding connections without failures Applied Materials External
Slide 22: High Technology Complexity Across Front-End and Packaging
High Technology Complexity Across Front-End and Packaging Step-to-step Angstrom-era Industrial Scale Speed Innovation-to- Interactions Precision Angstrom-era Commercialization time Performance, Yield, Productivity (incl. variability control) Applied Materials External
Slide 23: Applied's Unique Connectivity Strategy to Solve Complexity
Applied’s Unique Connectivity Strategy to Solve Complexity Connecting Connecting Connecting Products, Customers, 3 Ecosystem Innovators Partners in one place Guided by our unique Co-development with Earlier, deeper, faster innovators with integration Customer R&D leaders collaboration enabled by and
Slide 24: Applied's Unique Portfolio: Enables Connecting Technologies
Applied’s Unique Portfolio: Enables Connecting Technologies BROADEST CAPABILITIES Applied Competitors ALD ✓ ✓ ✓ ✓ Bonding ✓ Cleans ✓ ✓ #1 CMP ✓ #1 CVD ✓ ✓ ✓ ✓ ✓ ECD ✓ ✓ #1 Epitaxy ✓ ✓ Etch ✓ ✓ ✓ ✓ Furnace ✓ #1 Implant ✓ Lithography ✓ M&I (optical) ✓ ✓ #1 M&I (eBeam) ✓ ✓ ✓ #1 PVD ✓ ✓ Thermal ✓ ✓ Trac
Slide 25: Applied's Unique Portfolio: Enables Connecting Technologies
Applied’s Unique Portfolio: Enables Connecting Technologies BROADEST CAPABILITIES UNIQUE INNOVATORS Applied Competitors ALD ✓ ✓ ✓ ✓ Bonding ✓ Materials Cleans ✓ ✓ CMP ✓ Equipment CVD ✓ ✓ ✓ ✓ ✓ ECD ✓ ✓ Process Technology Epitaxy ✓ ✓ Etch ✓ ✓ ✓ ✓ Furnace ✓ Device Implant ✓ Lithography ✓ Systems M&I (o
Slide 26: Applied's Unique Portfolio: Enables Connecting Technologies
Applied’s Unique Portfolio: Enables Connecting Technologies BROADEST CAPABILITIES UNIQUE COMBINATIONS Applied Competitors Unit ALD ✓ ✓ ✓ ✓ Process Tools Bonding ✓ Cleans ✓ ✓ CMP ✓ Co-optimized CVD ✓ ✓ ✓ ✓ ✓ Solutions ECD ✓ ✓ Epitaxy ✓ ✓ Etch ✓ ✓ ✓ ✓ Integrated Materials Furnace ✓ Solutions Implant ✓
Slide 27: Co-optimization and Integration Improves Resistance, Speed, Power
Co-optimization and Integration Improves Resistance, Speed, Power Clean Deposition hardmask Epi Epi Deposition patterning film Co-optimized etch Track photoresist Contact Resistance and deposition Lithography trench pattern Silicon Interface processes Lithography contact pattern Epi Epi Etch pattern
Slide 28: Connecting Process and Metrology: Void-Free Epi Growth
Product Connecting Process and Metrology → Void-Free Epi Growth Launch SiGe Recess PROVision See-Through Imaging >50kV + <15kV >50kV CFE resolution GAA (100nm) Side View Top View Source: Applied PROVision and Xtera co-optimization for void-free uniform growth Provision metrology for S/D Epitaxy • Un
Slide 29: Applied's Unique Portfolio: Connecting Partner Technologies
Applied’s Unique Portfolio: Connecting Partner Technologies 2 BROADEST CAPABILITIES UNIQUE COMBINATIONS Applied Competitors Unit ALD ✓ ✓ ✓ ✓ Process Tools Bonding partner ✓ Cleans partner ✓ ✓ CMP ✓ Co-optimized CVD ✓ ✓ ✓ ✓ ✓ Solutions ECD ✓ ✓ Epitaxy ✓ ✓ Etch ✓ ✓ ✓ ✓ Integrated Materials Furnace par
Slide 30: Connecting Partners' Technologies: Co-optimized and Integrated
Connecting Partners’ Technologies: Co-optimized and Integrated Die to Wafer Hybrid Bonding Co-optimized Not Optimized + Integrated Bonding CVD Bonding CVD Pad Etch Warpage modulation Applied + BESI Pad Etch Barrier / Seed Barrier / Seed Partnership Cu ECP Cu ECP CMP Wet clean w/ carrier CMP Dicing D
Slide 31: Value of Joint Integrated Processes: Bond Strength and Yield
Product Value of Joint Integrated Processes: Bond Strength and Yield Launch 6 steps all integrated in one tool Mitigating queue-time for higher yield Contamination risk Queue time issues Failing ✓ Yielding Cu Cu-Cu Integrated Gap UV release metrology Cu Wet clean w/o carrier Wet clean w/carrier Be
Slide 32: Complexity: Slow Innovation-to-Commercialization Cycle
Complexity: Slow Innovation-to-Commercialization Cycle “UNIVERSITY ENVIRONMENT” EQUIPMENT COMPANY CHIPMAKER Commercial Technology Technology Commercial Proof of Equipment & Integrated into Integrated into Chip Idea Concept Process Module Device 5 – 7 YEARS 2 – 3 YEARS 1 – 2 YEARS 1 – 2 YEARS 1 – 2 Y
Slide 33: Connecting Ecosystem + Connecting Them in One Place
2023 Connecting Ecosystem + Connecting Them in One Place New R&D Center Universities Equipment peers Opening 2026 Innovation Suppliers R&D Consortia First access to new materials Network innovations (years before anyplace else) Highest velocity co-innovation – critical to win the race for new chip
Slide 34: EPIC Center Will Enable Faster Innovation and Commercialization
EPIC Center Will Enable Faster Innovation and Commercialization “UNIVERSITY ENVIRONMENT” EQUIPMENT COMPANY CHIPMAKER Commercial Technology Technology Commercial Proof of Equipment & Integrated into Integrated into Chip Idea Concept Process Module Device 5 – 7 YEARS 2 – 3 YEARS 1 – 2 YEARS 1 – 2 YEAR
Slide 35: Complexity Recap Solving Complexity
Complexity Recap Solving Complexity Connecting Products, Innovators Connecting Customers, Partners Connecting Ecosystem in one place Applied Materials External
Slide 36: New Products Seeing Strong Customer Adoption
Product New Products Seeing Strong Customer Adoption Launch Applied Centura Xtera Epi PROVision 10 eBeam Metrology Kinex Integrated Die-to-Wafer Hybrid Bonding System Cold Field Emission Enables void-free fill at ≤2nm nodes On-device 0.95nm see-through resolution 10-20X queue time bond quality,
Slide 37: Enablement
Enablement Mukund Srinivasan, Ph.D. Vice President and General Manager, Semiconductor Products Group OCTOBER 7, 2025 Applied Materials External
Slide 38: Recap on Enabling AI Everywhere
Recap on Enabling AI Everywhere Jim Chambers Rose Castanares Vice President, NVIDIA President, TSMC Arizona AI is the fifth industrial revolution, AI is everywhere, and its growth is driving transforming every industry exponential power demand AI’s demand drives nonstop innovation in Advanced logic
Slide 39: The Industry Must Deliver: More Compute, More Bandwidth, Less Energy
Semiconductor Devices are Enabling AI Improvements are Needed for Energy Efficiency The Industry Must Deliver: More Compute, More Bandwidth, Less Energy – Faster Applied Materials External
Slide 40: 3D Architecture Inflections Will Unlock AI Potential
3D Architecture Inflections Will Unlock AI Potential AI Leading-edge Logic AI DRAM: HBM + Leading Edge AI Sys. Integration GAA Backside High Bandwidth Vertical Advanced Transistor 3D DRAM Power Memory Transistor Packaging 30% power, 30% density Bandwidth +1,000% EEP +15% EEP +15% 1000x IO / mm
Slide 41: Priorities for Next-Generation AI Device Enablement
Priorities for Next-Generation AI Device Enablement SILICON ENABLEMENT PACKAGE ENABLEMENT FAB ENABLEMENT LOGIC DRAM Transistor Interconnect 4F2 2.5D and 3D Integration R&D and Ramp Acceleration Scaling Scaling VT Applied Materials External
Slide 42: Enablement Expert Panel
Enablement Expert Panel SILICON ENABLEMENT PACKAGE ENABLEMENT FAB ENABLEMENT Bala Haran, Ph.D. Subi Kengeri Mike Chudzik, Ph.D. Steve Frezon Vice President Vice President Vice President Vice President Integrated Materials Solutions General Manager Technology Customer Services & Support Semiconductor
Slide 43: Silicon Enablement
Silicon Enablement Bala Haran, Ph.D. Vice President, Integrated Materials Solutions, Semiconductor Products Group OCTOBER 7, 2025 Applied Materials External
Slide 44: Silicon Enablement Roadmap
Silicon Enablement Roadmap N P N P LOGIC GAA: gate-all-around CFET: complementary field effect transistor GAA GAA with GAA with CFET Backside Power Isolation DRAM RCAT: recessed channel array transistor BCAT: buried channel array transistor 8F2 6F2 4F2 3D DRAM VT: vertical transistor RCAT BCAT VT Ap
Slide 45: Key Levers for Energy Efficient Compute
Key Levers for Energy Efficient Compute VDD Resistance Capacitance Thermals 2 Pdynamic = α C VDD f Pdynamic : power consumed to perform operations VDD : supply voltage α : activity factor f : clock frequency C : capacitance Applied Materials External
Slide 46: Voltage Reduction with GAA
Voltage Reduction with GAA 30% 150 mV Dynamic Power Lower VDD FinFET GAA Applied Materials enables >50% of the process steps required for GAA FinFET : fin field effect transistor Applied Materials External GAA: gate-all-around
Slide 47: Voltage Variability Reduction
Voltage Variability Reduction VDD Variability Etch Profile Control Metrology Monitoring AIX Monitoring VDDMIN Variable gate lengths Uniform Massive measurements gate across entire wafer VDDMIN lengths Top-to-bottom CD variation translates to gate and channel length variation Wafer-level to fleet-lev
Slide 48: Resistance Total = FEOL + MOL + BEOL
RBEOL ResistanceTOTAL = RFEOL + RMOL + RBEOL RMOL RFEOL FEOL: Front End of Line (Transistor) MOL: Middle End of Line (Contact & Local Interconnect) BEOL: Back End of Line (Interconnect Wiring) Applied Materials External
Slide 49: Resistance FEOL: Precision Epitaxy and Massive Metrology
Resistance FEOL | Precision Epitaxy and Massive Metrology GAA S/D Epi @ ≤ 2nm Node CFE eBeam Uneven cell-to-cell ✓ Uniform growth cell-to-cell growth Voids ✓ No voids Conventional Epi PROVision 10 Xtera Epi Uniform void-free epitaxy co-optimized using fast scalable metrology CFE : cold field emissio
Slide 50: Resistance MOL: Integrated Solutions to Lower Resistance
Resistance MOL | Integrated Solutions to Lower Resistance GAA Contact Junction GAA Contact Metal Clean Contact Resistance Node Contact Silicon Interface Deposition hardmask ~7 nm: Liner with Cobalt Deposition patterning film 50% 2 nm: Selective Tungsten Co-optimized etch Track photoresist <2 nm: Sel
Slide 51: Resistance BEOL: Reclaiming Conductivity for AI Performance
Resistance BEOL | Reclaiming Conductivity for AI Performance End-to-End Metals Co-optimization PVD Selective ALD CVD Interconnects Liners/Barriers Endura IMS >750 miles of wiring in PVD PVD an AI GPU processor Reflow Reflow On-Board Seam/Void-free Metrology >20 layers stacked copper ALD Gapfill ALD
Slide 52: Capacitance: Engineered with Advanced Materials and Processes
Capacitance | Engineered with Advanced Materials and Processes FEOL BEOL Enhanced Black Diamond Low- Dielectric Film Bottom Dielectric Isolation (BDI) Low- Opta CMP Dielectric Co-optimized CVD + Advanced Treatment + Etch Connected Technologies Lower Capacitance to Cut Dynamic Power Losses Applied
Slide 53: Thermal Management Key in 3D Integrated Circuits
Thermal Management Key in 3D Integrated Circuits Excessive heat degrades chip PREVENTION MANAGEMENT performance (frequency, Ion) System-Level Solutions Co-design removal paths Low VDD New Materials Improved thermal conduction Diamond Material X Thermal Conductivity Cu Material Y Low R Si High therma
Slide 54: Memory: Key Levers for Energy Efficient Compute
Memory | Key Levers for Energy Efficient Compute Capacity Bandwidth Speed 0110010110 2F 10110011010010010011 01100101101110100011 1011001101 2F Applied Materials External
Slide 55: Materials, Etch and Metrology Innovations Enable Capacitor Scaling
Materials Etch and Metrology Innovations Enable Capacitor Scaling Draco : New hard mask material New high temp etch technology Unique metrology (Higher modulus and selectivity) + (Better profile and CD uniformity) + (Faster and better sampling error) Si New Material Draco varying hole size 1.3x low
Slide 56: Architectural Innovation to Scale DRAM Density
Architectural Innovation to Scale DRAM Density 6F2 4F2 BCAT Transistor Vertical Transistor Challenge Solution High aspect ratio vertical Sym3 Z Etch channel profiles Interface traps Centura RPO + RTH RPO: remote plasma oxidation, RTH: rapid thermal processing with H2 Main Gate Shared Back Gate Gate
Slide 57: DRAM Speed & Performance
DRAM Speed & Performance Interconnect Black Diamond Low-k Cu Interconnect Advanced ULK Cu Cobalt Seed Enhancement Interconnects Cobalt Cap Transistor Celera SiN PECVD Poly Gate HKMG FinFET eSiGe Transistor w/ Embedded SiGe Stress Films Applied’s leading innovations in logic being Adopted in memory A
Slide 58: Package Enablement
Package Enablement Subi Kengeri Vice President and General Manger, Systems to Materials OCTOBER 7, 2025 Applied Materials External
Slide 59: Packaging Complexity in the AI Era
Packaging Complexity in the AI Era STATE-OF-THE-ART STATE-OF-THE-ART FUTURE Server Processor AI GPU System-in-Package PCF: 1 PCF: ~32,000 PCF: >600,000 Package size: ~50x50mm2 Package size: 2X Package size: 9X Silicon area: ~100mm2 Silicon area: 160X Silicon area: >>600X # of dies: 1 # of dies: 118
Slide 60: Hybrid Bonding for Lower Power and Higher Bandwidth
Hybrid Bonding for Lower Power and Higher Bandwidth Hybrid Bonds 10,000 to 1M I/O / mm2 Power: >0.05pJ / bit I/O density (finer pitch) Microbumps <1,000 I/O / mm2 Power: >0.5pJ / bit Power efficiency (lower interconnect length) I/O: Input / Output Applied Materials External
Slide 61: Hybrid Bonding Requires Co-Optimization and Integration
Hybrid Bonding Requires Co-Optimization and Integration Conventional Flow Cu-Cu Gap Simplified, for 2 wafers Ambient Ambient Ambient Ambient Cu Cu Cu-pads Wet Oxide Wet clean Plasma UV clean w/ Bonding Metrology + Dicing w/o carrier activation release Contamination risk CVD carrier Queue time issues
Slide 62: Applied Kinex Integrated Die-to-Wafer Hybrid Bonding System
Applied Kinex Integrated Die-to-Wafer Hybrid Bonding System Industry’s First Integrated Die-to-Wafer Hybrid Bonding System ✓ Software-enabled chiplet management system supports traceability and binning requirements ✓ Integration maximizes yield through particle prevention, queue time optimization, a
Slide 63: Industry Leading End-to-End Portfolio of Hybrid Bonding Solutions
Industry Leading End-to-End Portfolio of Hybrid Bonding Solutions Producer CVD Sym3 Etch Endura PVD Nokota ECD Opta CMP Sym3 Etch Co-optimized + Integrated Bonding CVD Dielectric Stack Damascene RDL/Pad Barrier / Seed PVD Copper Pad Fill CMP with Tuned Wafer Singulation Warpage Modulation CVD Format
Slide 64: System-to-Materials Co-Optimization Platform for Advanced Packaging
Applied’s System-to-Materials Co-Optimization Platform for Advanced Packaging Enablement TSV 1 Hybrid Bonding 4 3 Micro Bump CHIP 1 CHIP 2 2 1 2 3 4 Micro Level Advanced Packaging/System Die Boundary Modeling Substrate Modeling Level Modeling Modeling Advanced modeling capability to solve the unique
Slide 65: Future Packaging Technology
Future Packaging Technology HBM Hybrid Bonding + 3.5D IC Chiplets Stacking + Co-Packaged Optics + Large Interposers + Bridges + Passives + Panels + Glass Applied’s Broad Portfolio + EPIC Platform = Faster Packaging Innovation Applied Materials External
Slide 66: Fab Enablement: R&D Acceleration
Fab Enablement R&D Acceleration Mike Chudzik, Ph.D. Vice President of Technology, Semiconductor Products Group OCTOBER 7, 2025 Applied Materials External
Slide 67: R&D Acceleration Enablers
R&D Acceleration Enablers Largest Tool Portfolio Digital Tools: AIx Co-Optimized Modules EPIC Platform Process and Metrology CREATE: CVD, PVD, ALD, Plating, Epitaxy, Selective Deposition SHAPE: Etch, CMP, Sel. Removal, Pattern Shaping MODIFY: Implants, Thermal, Treatments, Oxidation ANALYZE: Optical
Slide 68: From Tungsten to Moly Leadership in Contact Scaling
From Tungsten to Moly Leadership in Contact Scaling Contact Fill with Liners Liner-free Selective Fill >10nm 7nm-3nm 3nm-2nm <2nm W Co W Mo W Co W Mo Interconnects TiSi TiSi TiSi TiSi Si / SiGe Si / SiGe Si / SiGe Si / SiGe W → Co Co → W W → Mo Contact Metal Layers Transistors 1 Trillion contacts ac
Slide 69: Mo Contacts: Process + Metrology + Digital Tools for Speed
Mo Contacts: Process + Metrology + Digital Tools for Speed Endura PVD Cross-Sectional Opta CMP Cross-Sectional Electrical Testing: TEM~1-2 sites TEM: ~1-2 sites >1,000 sites overfill underfill protrusion dishing Moly Deposition Moly CMP (Weeks Later) TRADITIONAL LEARNING CYCLE Close the Loop in Endu
Slide 70: Co-Optimized Modules to Save Months of Development Time
Co-Optimized Modules to Save Months of Development Time Tool Tool Tool Startup and Module Development Production Demo / Selection Order / Build Qualification at Customer Site Ramp Early –Access Module Development Module Demo Device ~ 3 0 % T I M E S AV E D Specification Technologies at Applied Mater
Slide 71: Applied EPIC Platform – IP Secure High Velocity Co-Innovation
Applied EPIC Platform – IP Secure High Velocity Co-Innovation Satellite Labs Focused themes META Maydan Center Process Integration Leading Edge Si Process EPIC Center On-site collaboration Leading Edge Processes & Tools APDC Wafer & Die Packaging Customer-like IP Security Test Vehicles Locked down r
Slide 72: R&D Acceleration Enablers
R&D Acceleration Enablers Largest Tool Portfolio Digital Tools: AIx Co-Optimized Modules EPIC Platform Process and Metrology CREATE: CVD, PVD, ALD, Plating, Epitaxy, Selective Deposition SHAPE: Etch, CMP, Sel. Removal, Pattern Shaping MODIFY: Implants, Thermal, Treatments, Oxidation ANALYZE: Optical
Slide 73: Fab Enablement: Manufacturing Ramp Acceleration
Fab Enablement Manufacturing Ramp Acceleration Steve Frezon Vice President, Customer Services and Support, Applied Global Services OCTOBER 7, 2025 Applied Materials External
Slide 74: High Velocity Commercialization
High Velocity Commercialization HIGH VELOCITY CO- INNOVATION HIGH VELOCITY COMMERCIALIZATION TIME TO MARKET R&D RAMP HVM Golden Tool Atomic-level Precision Needed at Industrial Scale Applied Materials External
Slide 75: Accelerating Time to Market
Accelerating Time to Market TIME TO MARKET R&D RAMP HVM YIELD OUTPUT Golden Tool COST Atomic-level Precision Needed at Industrial Scale Applied Materials External
Slide 76: Service Innovation – Accelerating Time to Market
Service Innovation – Accelerating Time to Market AI IN THE FAB ACCELERATE Results Applied Solutions R&D Time to qualify AI X AppliedPRO Process window Ramp Time to match CrossMatch Yield optimization HVM Yield Defect Expert System Output FleetOptimizer Cost of ownership Predictive Maintenance Action
Slide 77: Service Innovation - First Time Right CrossMatch
AIX Service Innovation - First Time Right CrossMatch Matching at angstrom level precision KEY PARAMETERS Critical Dimensions Linearity Uniformity Resistance Profile Angle Stress Zonal Profiles Defects TIME TO MATCH >50% reduction LAB FAB A FAB B Accelerating Performance & Yield Before CrossMatch Aft
Slide 78: Service Innovation - Reduce Variability for Higher Yield & Output
AIX Service Innovation - Reduce Variability for Higher Yield & Output Components PM Engineering AppliedPRO EPI Etch & CVD CVD >30% Uniformity Improvement Green-to-green Improvement Centering Process Window Uniformity Before After Etch CVD 3 sigma 1.23% 0.81% Operation 160 90 140 Component Before Etc
Slide 79: Service Innovation – Increasing Output
AIX Service Innovation – Increasing Output AIX ‒CONNECTED TOOLS HIGHER OUTPUT Global Network 30% SECURE CONNECTIVITY FASTER RESOLUTION non-AIX AIX Average Resolution Time (Quarterly) Accelerating time to resolution Applied Materials External
Slide 80: Accelerating Commercialization Together
Accelerating Commercialization Together Faster Time to Market in the AI Era Applied Materials External
Slide 81: Growing our Opportunity and Share
Growing our Opportunity and Share Prabu Raja, Ph.D. President, Semiconductor Products Group OCTOBER 7, 2025 Applied Materials External
Slide 82: Strong Global Fab Investments Outlook
Strong Global Fab Investments Outlook Active Fab Projects* >100 Worldwide *Projects under operation / equipping / construction / planning Applied Materials External
Slide 83: Device Inflections Enabled by Materials Engineering
Device Inflections Enabled by Materials Engineering Applied Materials External
Slide 84: Expect Materials Engineering to Increase within WFE Mix
Expect Materials Engineering to Increase within WFE Mix Materials Engineering vs. Litho/Track WFE Mix* LOGIC DRAM 100% Litho/Track Materials Engineering 0% 20nm+ 16/14nm 7nm 5/4nm 3nm GAA+BPD D1a D1b D1c D1d VT 4F2 3D DRAM Materials engr % of incremental WFE* >50% >40% >40% >60% >75% >60% >70% >40%
Slide 85: Device Inflection Growth Opportunities
Device Inflection Growth Opportunities LEADING-EDGE LOGIC ADVANCED DRAM Several pts share gain | +30% Revenue Oppty.* Several pts share gain | +30% Revenue Oppty.* + 10pts share in over 10 years $14B $12B $7.5B SAM Growth $6B $6.5B SAM Growth FinFET 2nm GAA 14A GAA 6F2 4F2 3D DRAM with BSPDN with BS
Slide 86: Strong Wafer Starts Growth Expected for Advanced Logic and DRAM
Strong Wafer Starts Growth Expected for Advanced Logic and DRAM 3,000 3,000 DRAM 2,500 2,500 Installed Wafers (K WSPM) Installed Wafers (K WSPM) Leading-Logic 2,000 (≤7nm) 2,000 1,500 1,500 NAND 1,000 1,000 500 500 0 0 2020 2025 2030 2020 2025 2030 New additions at 3nm and below nodes DRAM: Expandin
Slide 87: Packaging Offers Key Growth Opportunity
Packaging Offers Key Growth Opportunity Industry’s broadest and most connected Advanced Packaging heterogeneous integration portfolio Revenue Extends Applied’s leadership in on-chip wiring to off-chip wiring (#1 overall, #1 in HBM) ~$1.7B Building a leadership portfolio for emerging ~$1.1B hybrid bo
Slide 88: Sustained, Profitable Growth through PPACt Services
Sustained, Profitable Growth through PPACt Services AGS Revenue $B >10% CAGR ‘20-’24 >2/3 of core AGS revenue from subscriptions >18K tools under Service Agreements 6.2 4.2 >90% Renewal Rate FY'20 FY'24 Helping customers manage technology complexity in the AI-era drives growth for AGS Applied Materi
Slide 89: Applied Well Positioned to Grow with AI Mega Trend
Applied Well Positioned to Grow with AI Mega Trend Market from AI Nodal SAM from Share, service silicon content device inflections by solving key HVPs >100 active fab projects Logic and DRAM SAM Several pts share Wafer starts AGS growth ▪ Unique connectivity strategy (addresses high techno
Slide 90: 2025 SEMICON West Technology Breakfast
SS 2025 SEMICON WEST Technology Breakfast ~* @ APPLIED MATERIALS...
Applied Materials — 2025 SEMICON West Technology Breakfast on 6ix