Asml Holding Nv · EURONEXT:ASML
Asml Holding Nv — Investor Day (November 2003)
24 slides from Asml Holding Nv's investor day presentation, Nov 13, 2003
Slide 1: Optical Maskless Lithography
Optical Maskless Lithography Bert Koek November 13, 2003 / Slide 1
Slide 2: Safe Harbor
Safe Harbor “Safe Harbor” Statement under the U.S. Private Securities Litigation Reform Act of 1995: the matters discussed during this presentation include forward-looking statements that are subject to risks and uncertainties including, but not limited to, economic conditions, product and pricing,
Slide 3: Optical Maskless Lithography
Optical Maskless Lithography l Margins in Semiconductor industry can vary significantly l Margins can be Influenced by: l Time to Market: Premium price for better performance or new application l Cost control: Lower overall production cost l ASML defined a concept based on Maskless Lithography where
Slide 4: Device introduction activity flow
Device introduction activity flow Design Introduction Mask Respin >18 months Start Design Release Mask making Release Mask Respin Long lead times in Release: 45% Many iterations 40% Respin reasons 35% Complicated simulations 30% Limited early proto typing 25% 20% 15% Mask Respin: 10% 5% Additional c
Slide 5: Escalating Mask Set Cost for future technology nodes
Escalating Mask Set Cost for future technology nodes Mask Set Cost (Current estimate, volume cost may be lower) $4,000,000 Technology Mask Set Price $3,500,000 0.18um 250,000 0.13um 640,000 $3,000,000 0.090um 1550000 Set Cost 0.065um $2,500,000 3750000 $2,000,000 $1,500,000 $1,000,000 $500,000 $0 0.
Slide 6: How optical mask-less helps
How optical mask-less helps Design Introduction Mask Respin >18 months Start Design Release Mask making Release Mask Respin Start Design Release Release < 12 months • Mask-less technology reduces: - Release and mask making cycle time - Cost for proto typing and Mask Respin / Slide 6
Slide 7: Overview
Overview l ASML and Micronic started 2.5 years ago a joint study program to explore the feasibility of maskless lithography based on the technology of both companies. l ASML and Micronic have concluded based on this study: a - 5Wph - Optical Maskless Lithography Scanner is feasible for the 65nm node
Slide 8: Spatial light modulator in mask-less scanner
Spatial light modulator in mask-less scanner Micronic SLM chip 8 mm x 33mm active area 1.048 Mpixels (512 x 2048 pixels) Each pixel 16X16um2 / Slide 8
Slide 9: Productivity: Data Rate Impact
Productivity: Data Rate Impact l Productivity determined by data rate towards SLM l Array of individual SLM’s will be used l Assumptions: l 300mm Wafer size l 5 WPH 70 l 30nm Pixel size l Dual pass l 8 bits/pixel l Result: 200-300 Gbyte/s Printing 360 000 pages with text and images per second or fil
Slide 10: Data-Path: Principle of Loading and Writing a Pattern
Data-Path: Principle of Loading and Writing a Pattern 2. Break stripe into micro-stripes. Each 1. Break field into stripes. micro-stripe spans part of a row of SLMs in the array. 3. Load full micro-stripe into Micro-shot n Micro-shot n+1 Micro-shot n+2 each overlapping SLM’s sub- array controller. 4
Slide 11: Example: OPC with Gray Scaling (Prolith)
Example: OPC with Gray Scaling (Prolith) Without OPC Example shows lines on mirror grid. Off-grid lines achieved with Mirror Tilt different tilt angles. [mrad] 7 6 5 4 3 2 1 0 With OPC / Slide 11
Slide 12: The envisaged Maskless Lithography System (MLS)
The envisaged Maskless Lithography System (MLS) l Target specifications: l Platform: TWINSCAN l Throughput: 5 wph (300mm) l Technology: 193nm l Applicability: 65nm node l Expected system availability: l 3 years after start of project l Price: Comparable with conventional scanners / Slide 12
Slide 13: Foundry like mask life distribution (200 mm)
Foundry like mask life distribution (200 mm) 20% • Most masks see 24 wafers ( = one wafer lot), • ASIC industry is moving to “sub-lot” production. 18% • Industry is working to process single wafers. 16% 14% % Reticles 12% 10% 8% 6% 4% 2% 0% 1 10 100 1000 10000 100000 Wafers per Reticle • The average
Slide 14: Reticle use based on Foundry data
Reticle use based on Foundry data: 50% of reticles used to print 1% of wafers (200 mm); 1% 100% 90% 80% 70% For Maskless systems: cum. reticles 60% High wafer throughput is not needed to save significant reticle costs 50% 40% 30% 20% 10% 0% 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 6% cum. w afers
Slide 15: Mask Usage: Foundry
Mask Usage: Foundry Data Scaled to 20 kWSPM @ 200mm Expose 10 Critical Layers per Wafer using 1st 2nd 3rd Maskless Scanner >>>>>>>>>> 40 Cum. Mask Sets Used/Month 30 80% or 27 Mask Sets 20 Mean: 580 Wafers/Mask 50% or 17 Masks Sets Median: 20 Wafers/Mask 10 150 1000 0 1 10 100 300 600 1000 Expose 90
Slide 16: Mask-less practically eliminates fixed mask cost
Mask-less practically eliminates fixed mask cost Maskless Scanner Maskless more economical Cost per Mask Run Scanner ∝ 1/Tput(mask) = 1/100 Fixed cost of masks With mask Small Data ∝ 1/Tput(maskless) = 1/5-10 more economical Prep Cost Breakeven #Wafers 100-500 Wafers # Wafers / Slide 16
Slide 17: Maskless Economic Model: Input Parameters
Maskless Economic Model: Input Parameters l lMLS specifications: 5 W/hr; Tool Parameters l Tool Cost ($) $25,000,000 Suitable for 65 nm node l Throughput (wfr/hr) 5 l Utilization 50% lRealistic mix of maskless (critical layers) and mask- Mask Layers 20 20 20 20 based (non-critical layers) MLS Layers
Slide 18: Maskless Economic Justification: Reduction of annual reticle costs and customer ROI
Maskless Economic Justification: Reduction of annual reticle costs and customer ROI for 90nm Technology MLS MIRR (MLS vs. STD) 90nm MIRR on Number of Designs/Year If mask- price reduced to 30% 46% 41% 36% 29% 26% 21% 9% -10% MLS MIRR (MLS vs. STD) / Slide 18
Slide 19: Mask-less practically eliminates fixed mask cost
Mask-less practically eliminates fixed mask cost Maskless Scanner Cost per Mask Run Scanner ∝ 1/Tput(mask) = 1/100 Fixed cost Optimum operating area for production Fab of masks Small Data ∝ 1/Tput(maskless) = 1/5-10 Prep Cost # Wafers / Slide 19
Slide 20: Current Wafer Fab
Current Wafer Fab Regular scanners All designs All output All reticles All wafers wafers / Slide 20
Slide 21: The New Wafer Fab Philosophy
The New Wafer Fab Philosophy Regular scanners Verified high volume designs few reticles High volume most wafers wafers Low volume New designs few wafers and design prototype wafers New and low volume designs Maskless scanners / Slide 21
Slide 22: Maskless Rationale: Summary
Maskless Rationale : Summary l 1. Maskless is a solution for three problems in the Semiconductor industry: l Mask costs, l Time To Market: design to wafer l Eliminate a prohibiting cost factor for new designs l 2. Optical Maskless because of: l No fundamental throughput limitation l Compatible with
Slide 23: ASML strategy for Optical Maskless Lithography
ASML strategy for Optical Maskless Lithography l Basis Tool concept 5Wph - Optical Maskless Lithography Scanner for the 65nm node, based on Twinscan (ASML) and Sigma (Micronic) technology. l Subject to commitment of potential customers, ASML - Micronic will establish a Joint Venture to develop this
Slide 24: Commitment
Commitment