Vicor Corporation · NASDAQ:VICR
Vicor — Uptime Institute 2010
20 slides from Vicor's conference presentation, May 2010
Slide 1: Universal, Scalable Factorized Power Architecture for New Processors and Memory Loads
Universal, Scalable Factorized Power Architecture for New Processors and Memory Loads Uptime Institute, New York, NY, May 2010 Abstract: HPC (High Performance Computing) processors and memory loads continue to increase power demands at lower voltages while performance density and total cost of owner
Slide 2: The Cost of Power Inefficiency
The Cost of Power Inefficiency • Going from ‘A’ to ‘B’ – From AC to the load – the complete chain • Power is ‘lost’ – #1: Along the way (distribution losses, connector losses) – #2: Stepping down (conversion losses) • Leading to more heat and more cost e.g. 380VDC AC PFC Conversion Distribution Loss
Slide 3: More Heat, More Cost
More Heat, More Cost • More Heat – Larger, heavier heatsinks – More air-conditioning – Lower reliability – Larger, heavier systems, etc. • Higher Cost – Cost of the cooling system – Cost of electricity year after year ($/MWhr) – Cost of fuel (airborne systems) – ‘Total Cost of Ownership’ (TCO) • Wor
Slide 4: High Efficiency Power Distribution
High Efficiency Power Distribution • In large systems, transmission/distribution loss is a problem – Power loss is related to current2 (PLOSS = I2R) – So, keep the voltage high (current low), to as close to the load as possible • 12V is very high loss (connector loss, pcb distribution loss, etc.) •
Slide 5: HVDC Distribution Today
HVDC Distribution Today: • 350-400V in datacenters – Telecom (NTT, Hitachi, NEC, etc.) – Computing (Hitachi, LBNL, Intel, etc.) • 350-400V in rack – Computing (IBM Power6, Power 7, Cray CX1, Dell LC, Verari, etc.) • 270V in airframe – Aerospace (Raytheon, Lockheed Martin, Harris, etc.) • 48V in rack
Slide 6: High Efficiency Power Conversion
High Efficiency Power Conversion • Efficiency is driven by: – Topology • High efficiency building blocks – smaller, less heatsinking, even closer to the load – Minimum conversion stages (eliminate duplicate functions) • Choice of Topology is driven by: – System architect’s understanding of Total Cos
Slide 7: Factorized Power Architecture (FPA) and V•I Chips
Factorized Power Architecture (FPA) and V•I Chips • A power supply has 2 functions: Regulation & Voltage Transformation • In an old, traditional system (e.g. synch buck, forward, half-bridge) – Regulation & Voltage Transformation are connected – Difficult to improve performance, consolidation lead t
Slide 8: Why V•I Chip?
Why V•I Chip? V•I Chip Power Voltage Component ‘Factor’ Current Uptime Institute 2010 8
Slide 9: High Efficiency Bus Conversion
High Efficiency Bus Conversion • Bus Converter Module (BCM) – Isolated, unregulated – Voltage transformer / current multiplier • Sine Amplitude Converter Topology – ZVS, ZCS, >1Mhz switching frequency • 380V to 48V, 330W at 96.5% in only 1.1in2 Uptime Institute 2010 US and Foreign Patents and Patent
Slide 10: System Benefits: Light-Load Efficiency
System Benefits: Light-Load Efficiency 380 VDC – 48 VDC Efficiency 97% 1x 2x 3x 4x Efficiency (%) 96% 95% 94% 93% • 4x 325W BCMs in parallel (1,300W) 92% • BCMs enabled when needed 91% 90% – Like ‘phase-shedding’ 89% 88% • Optimizes low-load efficiency 87% – EPA solution 86% Simple Array (4x) 85% Ef
Slide 11: 48V to Regulated, <1V Options
48V to Regulated, <1V Options • Traditionally, 48V to ‘low voltage load’ conversion has been a 2-step approach – e.g. 48 - 12V with a ‘brick’ then 12 - xV with a synchronous buck converter • As load voltages decrease… – Processors now <1V (VR12 spec down to 0.5V), memory <1.2V … the ‘duty-cycle’ lim
Slide 12: Direct 48V-to-Load Conversion
Direct 48V-to-Load Conversion Pre-Regulator Module (PRM) Voltage Transformation Module (VTM) • Non–isolated, regulator • Isolated, voltage transformer • ZVS Buck – Boost Topology • Sine Amplitude Converter Topology – ZVS, >1MHz switching – ZVS, ZCS, >1Mhz switching frequency • Performance • Performa
Slide 13: Direct 48V-to-Intel Processor (VR12)
Direct 48V-to-Intel Processor (VR12) • ‘Voltage Regulator’ (VR) spec sets voltage for peak processor performance • FPA is a ‘pure power’ solution – Digital or analog loop – Any industry standard controller (with access to VID) – Re-use existing control / housekeeping solutions VTM PRM xV 48V P VF 13
Slide 14: The FPA Advantage
The FPA Advantage • Applying FPA to higher power systems highlights the size, efficiency and value of the V•I Chips • Efficiency ↑ 9% • Power Loss ↓ 45% • Size ↓ 45% • Save Money: –$30 per year, per processor –$600,000 per year, per datacenter • Save Energy (Oil) –2,600 barrels per year, per datacen
Slide 15: Cray 'CX1' / Dell 'LC' with V•I Chips
Cray ‘CX1’ / Dell ‘LC’ with V•I Chips • 380V to 12V with 2x 300W HV BCM bus converters 380V Æ12V Conversion Hot-swap, In-rush, etc. 2x 300W HV BCMs Uptime Institute 2010 15
Slide 16: IBM Blue Gene/P with V•I Chips
IBM Blue Gene/P with V•I Chips • Blue Gene/P with Vicor holds 12 of the top 20 in the Green500 (Mflops/Watt) • Direct 48V-to-load Conversion – 1x PRM +2x VTMs per card • 48V input, 1.2V output, 200A for processors and 1.8V, 160A for memory PRM Regulator VTM Transformers Uptime Institute 2010 16
Slide 17: IBM Power 7 with V•I Chips
IBM Power 7 with V•I Chips • PRM regulators ‘factorized’ away from VTM transformers – High efficiency distribution, high efficiency power conversion at load PRM Regulators VTM Transformers Uptime Institute 2010 17
Slide 18: IBM p7-IH (DARPA/PERCS) with V•I Chips
IBM p7-IH (DARPA/PERCS) with V•I Chips DC converter and Control Assembly “DCCA” 350VDC to 44V Regulated Output Using BCM, PRM V•I Chips 20 kW per board Node (top side) Node (bottom side) 8x POWER7 MCMs, DRAM, Optical hubs 44V to 1.xV using multiple 130A VTM V•I Chips Uptime Institute 2010 18
Slide 19: In Summary
Universal, Scalable Factorized Power Architecture for New Processors and Memory Loads In Summary: • The keys: – High(er) voltage distribution – High efficiency power converters – Intelligent exploitation of key features to achieve system benefits • FPA and V•I Chips – Highest system efficiency – Sma
Slide 20: Thank You
Thank You • What are your questions / comments? Stephen Oliver, Vicor [email protected], +1 978 749 3256 Uptime Institute 2010 20