Synopsys, Inc. · NASDAQ:SNPS
Synopsys — Technical Presentation (2012)
30 slides from Synopsys's technical presentation, May 9, 2012
Slide 1: UVM-based Random Verification through VCS and CustomSim in Analog Mixed-signal Designs
Universal Verification Methodology (UVM)-based Random Verification through VCS and CustomSim in Analog Mixed-signal Designs for Faster Coverage Closure Warren Anderson Ravi Ram AMD Vijay Akkaraju Synopsys
Slide 2: The Problem
The Problem • Full verification of analog+digital functions in a mixed-signal design • FastSPICE has significant limits: – Long sim times (12+ hours per test) results in: • Only a small fraction of regression run in mixed mode. (often less then 5%) • Significant coverage holes – Limited randomizatio
Slide 3: The Solution
The Solution Use Verilog-AMS for mixed signal models and simulations: • Pros: – Accuracy approaches SPICE – Simulation time >10x faster, better resulting in: • More tests run in mixed-signal mode. • More coverage points hit – Enables randomization on the analog side • Challenges – Development time f
Slide 4: Outline of this talk
Outline of this talk • Target design • Verification environment • Verilog-AMS models • Metrics and measurements • Summary and conclusions 4
Slide 5: Design
Design • PHY layer of an AMD APU processor DDR sub-system • Bidirectional bus between processor and DRAM memory • Analog circuits: – Output driver – Input receiver – Input line impedance termination – Calibration – Reference voltage generation and distribution – Current generation and distribution –
Slide 6: DDR PHY Design
DDR PHY Design ‘Controller interlace and Level Shiters Synopsys Users Group SILICON VALLEY 2012 -_ >| [7] Syeatrst i I ByeBindl a ] 4 sj | ‘ 1 tT | olka h> 4 OM_DastP) i ch NC_DOS1N _t— | | | 2 aaa _— 4 1 CBIODTs ¢ : OSfODTy ‘ Controt Command #3 je: Command / 4 Logic data out + Address! =: : Address
Slide 7: Outline of this talk
Outline of this talk • Target design • Verification environment • Verilog-AMS models • Metrics and measurements • Summary and conclusions 7
Slide 8: Universal Verification Methodology (UVM)
Universal Verification Methodology (UVM) • System Verilog based, industry standard verification methodology. – Maintained by, “Accellera” – standards organization for the EDA industry. • Developed to : – Increase design verification productivity by code re- use. – Optimize testbench and testcase dev
Slide 9: Verification Environment
Verification Environment • Adapted a UVM flow • Separate agent for each 32 bit channel • Each agent has an individual: – Sequencer – Driver – Monitor • Randomization: – Through a global config file – System Verilog constraint construct • Mixed-signal modeling: – Swap Verilog with a Verilog-AMS model
Slide 10: Verification Environment
Verification Environment 10 10
Slide 11: Randomization of analog portion using model parameters
Randomization of analog portion using model parameters • Goal: use UVM to configure the AMS model – AMS models use real variables to control behavior • Current LRM: – Real variable randomization not legal • Workaround flow: – Use System Verilog constraint construct for integers – Change SV constrain
Slide 12: Outline of this talk
Outline of this talk • Target design • Verification environment • Verilog-AMS models • Metrics and measurements • Summary and conclusions 12
Slide 13: Mixed Signal Coding Architecture
Mixed Signal Coding Architecture • Model structure is key to enable – Simple Verilog-AMS coding – Schematic equivalence checking • Design hierarchy for Verilog-AMS modules – Define Verilog-AMS module boundary around the analog function only • Place as much digital function as possible in digital-onl
Slide 14: Verilog-AMS Model Example
Verilog-AMS Model Example 14
Slide 15: Verilog-AMS Example: output driver
Verilog-AMS Example: output driver • Verilog-AMS model boundary selected to contain only the analog function – Driver pullup or pulldown individually • Hierarchy and pins match between schematic and Verilog-AMS model • Module represents a function to be characterized in SPICE simulations – Output fu
Slide 16: Verilog-AMS Example: output driver
Verilog-AMS Example: output driver parameter real Rbank = 240.0; // Resistance of bank, scalable across different drive strength banks integer BaseWeight = 64 * 3.5 / 2.0; // Unit of weight is the LSB of the binary legs real Rbank_unit = 240.0; // Unit cell used for calibration of the driver versus
Slide 17: Verilog-AMS Example: output driver
Verilog-AMS Example: output driver electrical pad_int; // Intermediate node between the pad and supply analog begin // Resistor portion V(PAD_VIO, pad_int) <+ I(PAD_VIO, pad_int) * Rint * Rscale; // Transistor portion I(pad_int, VSS) <+ Ncal_ena * Tscale * ( xivp4 * V(pad_int, VSS) + xivp3 * V(pad_i
Slide 18: UVM and Verilog-AMS Linkage
UVM and Verilog-AMS Linkage • Use UVM to randomize analog variables – Process, voltage, temperature sensitivity – Analog behavioral properties: offset, noise, INL real PFactorResProc = 1.0 from [0.9:1.12]; // Process factor for resistance process variation // Minimum value is max R, maximum value is
Slide 19: Model Fit: output driver
Model Fit: output driver Synopsys Users Group SILICON VALLEY 2012 LT TT | TT T TT T TT T TT T TT T J ta Z “FF,0C,minR 3 [— _ Solid: SPICE a —_ [— Dashed: AMS a + = f" = 4 zt | -<*~ TT, OC, typ R | % L oe" Z 2 2 —— J fo" —T r= LL WA ee J £ L— Vf eer SS, 100C, max R _| =} 4 5) - J, - _ 1 — VA 7 oe L_
Slide 20: Mixed signal coding philosophy
Mixed signal coding philosophy • Code only for end goal – Functional verification in this case • Write models to include only the behavior that has a functional impact – No need to model all behaviors that could be modeled • Edge rates • Delays • Bandwidth • Keeps the analog portion of the simulatio
Slide 21: Example: input receiver
Example: input receiver x2 Data Slice Dll_ClkData (½ rate clk) ESD CDM Low-speed DDR3 Device (even/odd) Dll_ClkDataX (½ rate clk) data D Q 0 Rx_RcvBypass Flyover Rx D Q Rx_RcvDataEven 1 DFE Retiming FF DFE 0 Ctrl RxIn_VIO + Folded-cascode D3 Mode (or RDQS RESD Strobe Data mode) + cml2cmos DFE - Δ Ct
Slide 22: Verilog-AMS Example: input receiver
Verilog-AMS Example: input receiver • Verilog-AMS model boundary selected to contain only the analog function – Receiver amplifier, mux switches, comparator, reference generator • Hierarchy and pins match • Module represents a function to be characterized in SPICE simulations – Amplifier function an
Slide 23: Code Example: receiver comparator
Code Example: receiver comparator module ddr_comparator(input p, input n, output out); real CmprOffset = 0.0m; //default real CmprHyst = 1.0m; //default real CmprDelay = 0.0; //default electrical p,n,vid; reg out; real threshhi = CmprOffset + (0.5*CmprHyst); real threshlo = CmprOffset - (0.5*CmprHys
Slide 24: Outline of this talk
Outline of this talk • Target design • Verification environment • Verilog-AMS models • Metrics and measurements • Summary and conclusions 24
Slide 25: V-AMS Vs Verilog simulation
V-AMS Vs Verilog simulation • Example: I/O driver signal to the DRAM – Voltage-mode driver with de-emphasis equalization – 8-bit data bursts 25
Slide 26: Verilog-AMS simulation results
Verilog-AMS simulation results 26
Slide 27: V-AMS Vs Spice simulation
V-AMS Vs Spice simulation Test Name Verilog-AMS FastSPICE Simulation wall-clock time wall clock time speed-up Output impedance 3 minutes 28 hours 560x calibration cycle Output driver 6 seconds 30 minutes 300x functionality 27
Slide 28: Outline of this talk
Outline of this talk • Target design • Verification environment • Verilog-AMS models • Metrics and measurements • Summary and conclusions 28
Slide 29: Summary and Conclusions
Summary and Conclusions • Verilog-AMS extremely beneficial to increase verification coverage in mixed-signal designs – Enables large number of functional test cases within a standard verification framework – Improved simulation time over FastSPICE – If models written correctly, accuracy loss compare
Slide 30: Next Steps
Next Steps • Apply Verilog-AMS models to more projects – Models can be re-used in many cases – Advantage that models can be put in place well before circuit design is completed • Add more variables to the Verilog-AMS randomization to increase verification test coverage • Enhance the environment when