Synopsys, Inc. · NASDAQ:SNPS

Synopsys — Technical Presentation (March 2012)

31 slides from Synopsys's technical presentation, Mar 26, 2012

  1. Slide 1: Synopsys Unveils 3D-IC Initiative

    Synopsys Unveils 3D-IC Initiative © Synopsys 2012 1

  2. Slide 2: Outline

    Outline • Today’s challenges • Emerging 3D-IC solutions • Unveiling Synopsys’ 3D-IC initiative © Synopsys 2012 2

  3. Slide 3: Today's Challenges

    Today’s Challenges • Need for increasing system-level flexibility in integrating multiple technologies, processes, IP • Moore’s Law ―2D‖ scaling is getting more difficult/expensive • Processor-memory bandwidth and latency are critical (e.g., mobile, networking) • Power management is key for all desi

  4. Slide 4: Emerging 3D-IC Technologies

    Emerging 3D-IC Technologies Terminology © Synopsys 2012 4

  5. Slide 5: Basic Configurations

    Emerging 3D-IC Technologies Basic Configurations • Die 1 and Die 2 examples: − SoC and Memory − Multiple SoC • Dies and silicon interposer can utilize different processes © Synopsys 2012 5

  6. Slide 6: Four Main Categories of "More than Moore"

    Emerging 3D-IC Technologies Four Main Categories of “More than Moore” • Very ―Hot‖ topic • Some consider it a technical & economic alternative to scaling Memory “Cube” Silicon Interposer • Others see 3D-IC complementing scaling, boosting integration and performance (Wide I/O) Memory “Cube” on Logic

  7. Slide 7: Almost Now: Hybrid Memory Cube

    Emerging 3D-IC Technologies Almost Now: Hybrid Memory “Cube” • Stack of memory tiers – 15X more bandwidth than DDR3 Die Thickness ~ 30 – 70% less power & 1/10 real estate of 2D-IC – Stackable on interposer • Adoption planned in Server and Networking markets (2012) • Role of EDA – Mostly DFT, RC ext

  8. Slide 8: Example: Xilinx Virtex 7-2000T

    Emerging 3D-IC Technologies Example: Xilinx Virtex 7-2000T © Synopsys 2012 8

  9. Slide 9: Example: Xilinx Virtex 7-2000T

    Emerging 3D-IC Technologies Example: Xilinx Virtex 7-2000T Die (flip-chip) Microbumps Interposer (with TSVs) C4 Interposer- to-package bumps Package BGA balls- to-PCB Source: L. Madden, Xilinx, 2011 © Synopsys 2012 9

  10. Slide 10: 2014: Memory Cube on Advanced Logic

    Emerging 3D-IC Technologies 2014: Memory “Cube” on Advanced Logic • 3 Challenges Memory Cube Over Logic – Cost: TSV manufacturing too high for most applications Memory Cube – Heat: poor vertical/lateral Connection to Logic dissipation (TSVs, µbumps, memory controllers) – Supply chain: needs time to

  11. Slide 11: 3D Stacks are Great, But...

    Emerging 3D-IC Technologies 3D Stacks are Great, But… • Cost overhead still not viable for most applications • Heat needs to be managed • Supply chain – Who does what? – Who takes ownership—and responsibility? • Area & power savings cannot be taken for granted – Depend on TSV number, size, and place

  12. Slide 12: A Phased Approach, to Begin With

    A Phased Approach, to Begin With 2.5D-IC, While Waiting for 3D-IC to Take off • Additional cost of silicon interposer, but… – Cheaper substrate – No TSV and wafer thinning on advanced processes – Much higher connectivity among die • No heat management burden • Simpler supply chain • Huge performance

  13. Slide 13: Synopsys Unveils 3D-IC Initiative

    Synopsys Unveils 3D-IC Initiative Under Embargo Until March 26th, 2012 © Synopsys 2012 13

  14. Slide 14: Comprehensive, Evolutionary, Collaborative

    Synopsys Unveils 3D-IC Initiative 3D-IC 3D- Initiative Comprehensive Evolutionary Collaborative © Synopsys 2012 14

  15. Slide 15: Comprehensive, Evolutionary, Collaborative

    Synopsys Unveils 3D-IC Initiative 3D-IC 3D- Initiative Comprehensive Evolutionary Collaborative © Synopsys 2012 15

  16. Slide 16: Comprehensive 3D-IC EDA Solution

    Comprehensive 3D-IC EDA Solution TCAD, Implementation, Analysis, Test Sentaurus StarRC Ultra IC Validator HSPICE Interconnect Extraction DRC/LVS Simulation DFTMAX DesignWare STAR IC Compiler Galaxy Custom Design-for-Test Memory System Place & Route Designer © Synopsys 2012 16

  17. Slide 17: 3D-IC EDA Solution

    Synopsys 3D-IC EDA Solution Sentaurus Interconnect Mfg. • Thermo-mechanical TSV Modeling stress analysis • Electrical variation DFTMAX/STAR Memory • TSV connectivity Design-for-Test checking w/JTAG • Test compression 3D-IC Design & Verification IC Compiler Physical • Multi-die bump & TSV floorplanni

  18. Slide 18: Comprehensive, Evolutionary, Collaborative

    Synopsys Unveils 3D-IC Initiative 3D-IC 3D- Initiative Comprehensive Evolutionary Collaborative © Synopsys 2012 18

  19. Slide 19: Evolutionary EDA for 3D-IC/2.5D Design

    Evolutionary EDA for 3D-IC/2.5D Design Example: Place & Route with IC Compiler Prepare Libraries Update libs for 3D-IC TSV/bump, attributes, ITF, etc. requirements Perform standard Initialize Floorplan floorplanning Place/Check/Assign/Connect/Route Additional 3D-IC Bumps/Lands/TSVs implementation st

  20. Slide 20: Evolutionary EDA: Detailed Place & Route Flow

    Evolutionary EDA for 3D-IC/2.5D Design Detailed Place & Route Flow Initialize Floorplan Check Die Interface Assign Flip- Flip-chip Nets for Each Die Inter-die physical Auto assign bump- contact alignment to-IO cell nets Place Frontside RDL Routing Bumps & Backside Place IO Cells (front-- & back- (fr

  21. Slide 21: Example: Parasitic Extraction with StarRC Ultra

    Evolutionary EDA for 3D-IC/2.5D Design Example: Parasitic Extraction with StarRC Ultra Silicon Interposer Stacked Die Face2Face Face2Back Substrate Substrate Die 1 Die 1 Die 2 Front Side Front Side μbumps μbumps Interposer BM1 BM1 Silicon Front Side Front Side M1 Back Side M1 Die 2 Substrate TSV Sub

  22. Slide 22: StarRC TSV Modeling Support

    Evolutionary EDA for 3D-IC/2.5D Design StarRC TSV Modeling Support Insulator M1 TSV <tsv_name> { FROM=<layer> TO=<layer> T RHO=<value> AREA=<value> Substrate S Substrate HEIGHT=<value> V DIEL_THICKNESS=<value> DIEL_ER=<value> BM CRT1=<value> CRT2=<value> } • Foundry qualified • StarRC computes R and

  23. Slide 23: Multi-Technology Circuit Simulation with HSPICE

    Evolutionary EDA for 3D-IC/2.5D Design Example: Multi-Technology Circuit Simulation with HSPICE Technology A: Technology B: - Models - Models - Corners Chip A Chip B - Corners - Parameters - Parameters Netlist A: Netlist B: - Devices - Devices - Nets - Nets - Subcircuits - Subcircuits • Support diff

  24. Slide 24: Multi-Technology Circuit Simulation with HSPICE

    Evolutionary EDA for 3D-IC/2.5D Design Example: Multi-Technology Circuit Simulation with HSPICE • New constructs for defining modules with separate scopes .module <label> – Unique IC module entities without name or .include <> circuit properties collision .lib <> .model <> • Master control over corn

  25. Slide 25: Comprehensive, Evolutionary, Collaborative

    Synopsys Unveils 3D-IC Initiative 3D-IC 3D- Initiative Comprehensive Evolutionary Collaborative © Synopsys 2012 25

  26. Slide 26: Industry Collaboration: TSV Stress Impact

    Synopsys Industry Collaboration TSV Stress Impact on Transistor Performance 6 1 Transverse Direction Longitudinal Direction 5 0 4 Delta ION (%) Delta ION (%) -1 3 P @Si P @Si P @model P @model 2 N @Si -2 N @Si N @model N @model 1 -3 0 -1 -4 0 5 10 15 20 25 0 5 10 15 20 25 Distance from TSV Along Y (

  27. Slide 27: Industry Collaboration: DFT Methodologies for 3D-IC

    Synopsys Industry Collaboration Exploring DFT Methodologies for 3D-IC 3D-IC Test Architecture © Synopsys 2012 27

  28. Slide 28: Summary

    Synopsys Unveils 3D-IC Initiative Summary • 3D-IC integration offers tangible benefits for performance, form factor and power • Higher integration with multiple stacked vertically, or in a side-by-side ―2.5D‖ configuration • Innovative way to deliver large-scale devices with favorable yield and reli

  29. Slide 29: Insight 3D-IC Articles

    Synopsys Insight 3D-IC Articles http://www.synopsys.com/Company/Publications/SynopsysInsight/Pages/default.aspx © Synopsys 2012 29

  30. Slide 30: SNUG Silicon Valley 3D-IC Presentations

    SNUG Silicon Valley March 27th, 2012 3D-IC Presentations • Going 3D by Evolution Michael Jackson Vice President of R&D, Physical Implementation, Synopsys • FPGAs with Stacked Silicon Interconnect Technology Shankar Lakka Director of IC Design, Xilinx • Synopsys Silicon Interposer Design Solution Fra

  31. Slide 31: Thank You

    Thank You synopsys’ 25: © Synopsys 2012 SyNOPSys’ 25:

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