Applied Materials, Inc. · NASDAQ:AMAT
Applied Materials — Investor Day (April 2022)
62 slides from Applied Materials's investor day presentation, Apr 21, 2022
Slide 1: New Ways to Shrink
New Ways to Shrink EXTENDING CLASSIC MOORE’S LAW SCALING AND APPLYING DTCO MASTER CLASS April 21, 2022 Applied Materials External 1
Slide 2: Forward-Looking Statements and Other Information
Forward-Looking Statements and Other Information Today’s presentations contain forward-looking statements, including those regarding anticipated growth and trends in our businesses and markets, industry outlooks and demand drivers, technology transitions, our business and financial performance and m
Slide 3: Welcome
2022 MASTER CLASSES WELCOME Michael Sullivan Corporate Vice President Head of Investor Relations NEW WAYS TO SHRINK MASTER CLASS | April 21, 2022 Applied Materials External 3
Slide 4: Battle of Exponentials Blog Series
“Battle of Exponential” Blog Series 600 Slope of Lines ~Growth Rates Semi Rev Data Growth 500 Trend CY00-15 Trend CY15-21E 400 Semiconductor Semi Industry ($, B) Semis Growth Battle of Revenue 300 Log Scale Exponentials Growth Inflection 200 Inflection 100 Classic 2D Scaling working well Diminished
Slide 5: PPACt: The New Playbook
The New Playbook Enabled by Key Inflections New ASICs and accelerators New architectures New memory / in-memory compute Specialty, CIS, power PERFORMANCE GAA transistors New structures / 3D Backside power distribution 3D NAND, 3D DRAM Gate PPACt New materials Contact Interconnect
Slide 6: 2024 Financial Model
2024 Financial Model FY’20 FY’24 MODEL LOW BASE HIGH Revenue $17.2B $23.4B $26.7B $31.0B Semi Systems $11.4B $16.2B $18.4B $21.7B Services $4.2B $5.6B $6.1B $6.7B Display $1.6B $1.6B $2.2B $2.7B GM% 45.1% 47.5% 48.5% 48.8% ADJUSTED* NON-GAAP OP% 26.3% 30.6% 32.4% 32.7% EPS $4.17 $7.00 $8.50 $10.00 2
Slide 7: 2022 Master Classes: New Ways to Shrink
2022 Master Classes APRIL 21 PERFORMANCE New Ways to Shrink PPACt POWER AREA-COST Applied Materials External
Slide 8: New Playbook for Power, Performance, Area-Cost and Time to Market
New Playbook for Power, Performance, Area-Cost and Time to Market Enabled by Key Inflections New ASICs and accelerators New architectures New memory / in-memory compute Specialty, CIS, power PERFORMANCE GAA transistors New structures / 3D Backside power distribution 3D NAND, 3D DRAM Ga
Slide 9: 2022 Master Classes: Wiring and Advanced Packaging
2022 Master Classes APRIL MAY 21 26* PERFORMANCE New Ways Wiring and to Shrink Advanced Packaging PPACt POWER AREA-COST * Target date, subject to change Applied Materials External
Slide 10: New Playbook for Power, Performance, Area-Cost and Time to Market
New Playbook for Power, Performance, Area-Cost and Time to Market Enabled by Key Inflections New ASICs and accelerators New architectures New memory / in-memory compute Specialty, CIS, power PERFORMANCE GAA transistors New structures / 3D Backside power distribution 3D NAND, 3D DRAM Ga
Slide 11: 2022 Master Classes: Subscriptions and Services
2022 Master Classes APRIL MAY 2H’22 21 26* PERFORMANCE New Ways Wiring and Subscriptions to Shrink Advanced and Packaging Services PPACt POWER AREA-COST * Target date, subject to change Applied Materials External
Slide 12: Agenda
Mike Sullivan AGENDA 9:00 PART 1 Welcome and Introduction Regina Freed Extending Classic Moore’s Law Scaling EUV Enablement with Novel Materials Engineering and AIx™ Ofer Adan 9:05 PART 2 3D Patterning Control Using eBeam Metrology to Solve Edge Placement Errors Uday Mitra, Ph.D. Beyond 2D Scaling D
Slide 13: Extending Classic Moore's Law Scaling: EUV Enablement
Extending Classic Moore’s Law Scaling: EUV Enablement with Novel Materials Engineering and AIx™ Regina Freed Corporate Vice President Semiconductor Products Group NEW WAYS TO SHRINK MASTER CLASS | April 21, 2022 Applied Materials External 13
Slide 14: Device Scaling Approaches
Device Scaling Approaches Contribution to Logic Density Scaling Intrinsic Scaling DTCO Intrinsic Scaling DTCO N N N+1 N+1 >50% >40% >25% 1% 16nm 10nm 7nm 5nm 3nm Source: M. Liu/tsmc, ISSCC 2021 DTCO: Design Technology Co-Optimization DTCO is becoming an increasingly important contributor to scaling
Slide 15: Pitch Scaling Continues
Pitch Scaling Continues 10 Materials-Enabled Scaling Era Resolution Limit K (λ/NA) g-line i-line 193i Litho Etch 80nm λ/NA / Minimum CD (µm) 1 DUV 193 (Dry) 193 (Immersion) SADP 40nm 0.1 0.18µm Litho Gap 90nm EUV SAQP 20nm 45nm High 22nm λ/NA NA 0.01 14nm 11nm EUV Litho Etch 25nm Min CD SADP 12.5nm
Slide 16: Applied Technologies that Enable EUV Patterning
Applied Technologies that Enable EUV Patterning High-Selectivity CVD Carbon Films Single-Chamber Etch and Deposition EUV Pattern Extension Diamond Etch Deposition Shaping + + + Si Increasing Hardness EUV Bridge Removal eBeam Metrology 3D Edge Placement Control AIx to accelerate R&D and widen process
Slide 17: Creating Patterns with EUV Lithography
Creating Patterns with EUV Lithography LINES / GRATING Create main pattern CUTS Segment lines VIAS Connect levels Applied Materials External
Slide 18: Patterning Control Challenges in EUV Lithography
Patterning Control Challenges in EUV Lithography ArF Litho ADI AEI EUV Litho Source: M. Smith et al., Proc of SPIE, 2009 >10X fewer Thinner resist Transfer layer, Small features, Smaller photons hardmask variability resist sensitivity features ArF: Argon Fluoride Applied Materials External
Slide 19: New CVD Carbon Films for EUV Pattern Transfer
New CVD Carbon Films for EUV Pattern Transfer ArF Litho Diamond Spin-On Films Increasing Hardness EUV Litho Applied Precision Stensar™ Advanced Patterning Film CVD Dense, high-selectivity layers Films Tunable stress for line variability control Film stack interface control improves yields Lo
Slide 20: Innovative Etch Technology Corrects Stochastic Errors
Innovative Etch Technology Corrects Stochastic Errors Rough EUV Single-chamber etch + dep technique Improved photoresist improves EUV photoresist patterns patterns CDU Improvement Applied Centris® Sym3® Y Etch 21% Alternate between deposition and etch in the same chamber Extensive pulsing modes
Slide 21: Directional Patterning Technology
Directional Patterning Technology EUV 1 EUV First half of All vias patterned desired pattern at minimum EUV spacing + Top View + Top View EUV EUV 2 Second half of Patterns desired pattern Extended = = Side View Final Final Pattern Pattern Applied Materials External
Slide 22: Directional Patterning: Stochastic Defect Removal
Directional Patterning: Stochastic Defect Removal EUV stochastic Directional defects cause patterning eliminates bridging bridge defects Source: Applied Materials RIE: Reactive Ion Etch Applied Materials External
Slide 23: Edge Placement: A Growing Challenge
Edge Placement: A Growing Challenge 3D metrology needed to overcome stochastic errors and process variability Applied Materials External
Slide 24: Actionable Insights (AIx) Accelerate Time to Solution
Actionable Insights (AIx) Accelerate Time to Solution Faster Better High Data Variety Actionable Data Scaling Actionable Data Insight and Results Proprietary Sensors Custom Metrology Process A B A Process B Deposition Etch Metrology Yield Loss Target Yield Loss AIx Analytics Platform Applied Materia
Slide 25: 3D Patterning Control Using eBeam Metrology
3D Patterning Control Using eBeam Metrology to Solve Edge Placement Errors Ofer Adan Senior Director Process Diagnostics and Control Group NEW WAYS TO SHRINK MASTER CLASS | April 21, 2022 25 Applied Materials External
Slide 26: Patterning Control Metrology Overview
Patterning Control Metrology Overview Chip eBeam Design Goals Measurements Tools Images 1. Pattern for each ADI: Optical overlay layer correctly transferred to Pattern centering VeritySEM® resist PROVision® CD uniformity 2. Pattern on resist correctly etched AEI: VeritySEM into wafer Correlation wit
Slide 27: EUV ADI Needs Lower eBeam Energy, Higher Pattern Resolution
EUV ADI Needs Lower eBeam Energy, Higher Pattern Resolution Challenge Feature DUV EUV Signal Contrast High Contrast Low Upcoming VeritySEM System High Resolution INNOVATIONat Low Energy Contrast High Applied Materials External
Slide 28: Pattern Fidelity from Development to Etch
Pattern Fidelity from Development to Etch EUV Patterning Stack Sources of Variability Resist Transfer Layer, Etch Hardmask Multilayer CDU Metrology Higher ADI-AEI Correlation Mean to target ADI step AEI step PROVision Y ield Loss Target Source: Cornel Bozdog, Micron Technology, Inc. (United States)
Slide 29: EUV Device Features >10X Smaller than Optical Overlay Targets
EUV Device Features >10X Smaller than Optical Overlay Targets Optical Proxy Target On-Die Features Source: EUV+SADP Applied Materials and IMEC Applied Materials External
Slide 30: Element 1: On-Device Metrology
Element 1: On-Device Metrology M1 M1 Via Cut Cut M2 Via M2 Via Optical Proxy Target On-Device eBeam Approximation Metrology Source: EUV+SADP Applied Materials and IMEC Applied Materials External
Slide 31: Element 2: Massive Across-Wafer Metrology
Element 2: Massive Across-Wafer Metrology Statistical Sampling Massive Measurements Applied Materials External
Slide 32: Element 3: 3D Integrative Metrology
Element 3: 3D Integrative Metrology Optical eBeam Optical Proxy Target 2D One Layer at a Time 3D Multilayer Approximation Low-Energy Multibeam High-Energy PROVision Feedback to Scanner Feedback to all EPE Sources Source: Applied Materials Source: EUV+SADP Applied Materials and IMEC Applied Materials
Slide 33: Applied PROVision 3E eBeam Metrology System
Applied PROVision 3E eBeam Metrology System Simultaneous, multilayer measurement of Edge Placement Error (EPE) all the contributors to yield-limiting EPE M1 ERROR SOURCES Overlay/alignment M1 M1 Via CD uniformity of lines Via Via CD uniformity of cuts Line roughness M2 M2 Pitch walking Cut
Slide 34: eBeam Technology Helps Accelerate the t in PPACt
eBeam Technology Helps Accelerate the “t” in PPACt R&D Transfer / Ramp High-Volume Acceleration Acceleration Manufacturing Acceleration Applied Customer Site Site Reducing the area between the curves is worth $billions Source: Applied Materials Applied Materials External
Slide 35: Beyond 2D Scaling: DTCO with GAA and Backside Power
Beyond 2D Scaling: DTCO with Gate-All-Around Transistors and Backside Power Distribution Uday Mitra, Ph.D. Vice President Semiconductor Products Group NEW WAYS TO SHRINK MASTER CLASS | April 21, 2022 Applied Materials External 35
Slide 36: Device Scaling Approaches
Device Scaling Approaches Contribution to Logic Density Scaling Intrinsic Scaling DTCO Intrinsic Scaling DTCO N N N+1 N+1 >50% >40% >25% 1% 16nm 10nm 7nm 5nm 3nm Source: M. Liu/tsmc, ISSCC 2021 DTCO: Design Technology Co-Optimization DTCO is becoming an increasingly important contributor to scaling
Slide 37: Transistor Density Scaling Over Time
Equivalent Channel Geometry Dennard Scaling Scaling Scaling 104 Standard Cell Inverter 103 High Density SRAM Logic Gates Transistor Density (Micro-Processors) 102 Relative Density 101 100 10-1 10-2 Strained Si Channel Doping, T ox , VDD Scaling Hi-k/Metal Gate FinFET 10-3 1970 1975 1980 1985 1990 19
Slide 38: Logic Scaling Continues with DTCO Innovations
Logic Scaling Continues with DTCO Innovations Equivalent Channel Geometry Dennard Scaling Scaling Scaling + DTCO 104 Standard Cell Inverter 103 High Density SRAM Logic Gates Transistor Density (Micro-Processors) 102 Relative Density 101 100 » Track height reduction » Fin depopulation 10-1 » Self-ali
Slide 39: Cell Area Reduction Through DTCO
Cell Area Reduction Through DTCO Contact 3 Fin Contact 2 Fin Single diffusion break Fin depopulation Contact over gate Applied Materials External
Slide 40: DTCO with Backside Power Distribution Network
DTCO with Backside Power Distribution Network Frontside power in Signal lines Over 10 metal layers Large voltage drop Power Signal Lines Power Power rail Transistor Si Power µ-TSV lines Area consumed for power delivery Power delivery Transistor Reduces power from 3-25%1 Power losses and area penalty
Slide 41: Area and Performance Scaling with Gate-All-Around
Area and Performance Scaling with Gate-All-Around (GAA) Reduces cell area by 20-30% Reduces leakage current FinFET GAA 120 GAA Ultra-Thin Straight Tapered Sub-Threshhold Sw ing (mV/dec) Nanowire FinFET FinFET FinFET Wfin 110 Width Lgate Min 7nm 15nm 5nm 18nm 7-8nm 22-24nm 7-10nm 28nm Structure 100 W
Slide 42: Key Steps in Gate-All-Around Fabrication
Key Steps in Gate-All-Around Fabrication … FinFET Fin Patterning Gate Patterning SD Recess pFET + nFET EPI Poly Removal High-k RMG GAA Nanosheet Gate Patterning SD Recess Inner Spacer pFET + nFET EPI Poly Removal + High-k RMG Patterning Recess Channel Release pFET: p-ty pe Transistor nFET: n-ty pe T
Slide 43: Epitaxial Steps in Gate-All-Around
Epitaxial Steps in Gate-All-Around Nanosheet Epitaxy - Abrupt Interfaces Alternate layers of Silicon and Silicon-Germanium Abrupt interfaces between layers is critical Growth Direction Needs low temperature in-situ surface preparation SiGe Relatively fast, non-selective EPI process Si Source
Slide 44: Selective Removal Steps in Gate-All-Around Fabrication
Selective Removal Steps in Gate-All-Around Fabrication Inner Spacer Recess Isolates the gate from the source / drain Tunable SiGe to Si selectivity precisely sculpts recess profile No damage to surrounding materials Channel Release Selective removal of SiGe defines channel width Extreme Si
Slide 45: Resuming Gate Oxide Scaling in Gate-All-Around Transistors
Resuming Gate Oxide Scaling in Gate-All-Around Transistors EOT scaling stalled EOT scaling thru interface engineering Critical transistor gate dimensions Conformal ALD and treatments Thinner gate oxide at equivalent leakage Hfin Lg W fin THK TIL 14 10 7 5* 3* TEM contrast Nitrogen distribution Node
Slide 46: Engineering All-Around Metal Gates in Narrow Geometries
Engineering All-Around Metal Gates in Narrow Geometries N-Metal FinFET Minimum CD Vt control through gate length P-Metal work function thickness tuning HK iL Channel NFET NFET PFET PFET Low Vt High Vt High Vt Low Vt N-Metal GAA Vt control through P-Metal HK volume-less dipole iL Minimum CD tuning na
Slide 47: Inspection and Process Control in 3D for Gate-All-Around
Inspection and Process Control in 3D for Gate-All-Around GAA process control challenges Measurements in 3D with electron beam see-through metrology 18 E-beam 16 Si source 14 L1 SiGe R1 eBeam Results 12 10 L2 R2 8 W3 W5 Volume 6 W7 W11 sampled 4 W12 W16 L3 R3 2 W17 W20 W21 0 0 2 4 6 8 10 12 14 16 18
Slide 48: Transistor Architecture Evolution after FinFET
Transistor Architecture Evolution after FinFET FinFET GAA Forksheet CFET Gate N Dielectric Wall N P N P P Si Fin Source: M. Bhuiyan, IBM, IEDM 2021 Transistor roadmap promises both area scaling and performance gains CFET: Complementary Field Effect Transistor Applied Materials External
Slide 49: Growth Opportunities in EUV Enablement, DTCO and Gate-All-Around
Growth Opportunities In EUV Enablement, DTCO and Gate-All-Around Raman Achutharaman, Ph.D. Group Vice President Semiconductor Products Group NEW WAYS TO SHRINK MASTER CLASS | April 21, 2022 Applied Materials External 49
Slide 50: Inflections Over Time
Inflections Over Time LONGER TERM EMERGING PERFORMANCE EXISTING PPACt POWER AREA-COST Applied Materials External
Slide 51: 2024 Financial Model
2024 Financial Model FY’20 FY’24 MODEL LOW BASE HIGH Revenue $17.2B $23.4B $26.7B $31.0B Semi Systems $11.4B $16.2B $18.4B $21.7B Services $4.2B $5.6B $6.1B $6.7B Display $1.6B $1.6B $2.2B $2.7B GM% 45.1% 47.5% 48.5% 48.8% ADJUSTED* NON-GAAP OP% 26.3% 30.6% 32.4% 32.7% EPS $4.17 $7.00 $8.50 $10.00 2
Slide 52: Semi Systems Revenue Growth Drivers
Semi Systems Revenue Growth Drivers CORE PPACt ENABLEMENT >100% >50% $6.5B $6.5B $4.8B FY’20 FY’24* FY’20 FY’24* *Represents 2024 Financial Model High Scenario Applied Materials External
Slide 53: The New Playbook
The New Playbook Enabled by Key Inflections New ASICs and accelerators New architectures New memory / in-memory compute Specialty, CIS, power PERFORMANCE GAA transistors New structures / 3D Backside power distribution 3D NAND, 3D DRAM Gate PPACt New materials Contact Interconnect
Slide 54: The New Playbook
The New Playbook Enabled by Key Inflections New ASICs and accelerators New architectures New memory / in-memory compute Specialty, CIS, power PERFORMANCE GAA transistors New structures / 3D Backside power distribution 3D NAND, 3D DRAM Gate PPACt New materials Contact Interconnect
Slide 55: Patterning Revenue Growth
Patterning Revenue Growth Applied’s DRAM and logic $M patterning markets 1,500 49% YoY » Etch, selective removal, CVD, ALD, CMP, thermal processing 1,000 35% CAGR Gaining patterning etch share 500 in the EUV inflection » +12 pts CY’15 CY’21 CY’15 CY’20 CY’21 Applied is #1 in DRAM Share: ~10%
Slide 56: Gate-All-Around Increases Revenue Opportunity
Gate-All-Around Increases Revenue Opportunity GAA increases Applied’s TAM TAM per 100K WSPM by >$1B per 100K WSPM capacity >$1B Broadest GAA portfolio » Epi » Selective removal » ALD » CMP » CVD » Implant » PVD » Thermal processing FinFET GAA » Etch » Process control Applied Materials External
Slide 57: Gate-All-Around – Epitaxy Opportunity
Gate-All-Around – Epitaxy Opportunity Two new expitaxy applications GAA Epi TAM, 100K WSPM » Rapid, blanket epitaxial deposition for GAA channel superlattice formation » Precise, selective epitaxial growth Selective for GAA channel source-drain engineering Blanket Applied Materials External
Slide 58: Gate-All-Around – Selective Materials Removal Opportunity
Gate-All-Around – Selective Materials Removal Opportunity Selective removal helps engineer channel width and uniformity » Key to chip power and performance Applied is capturing the majority of GAA selective etch positions 14nm 5nm GAA Industry leader with >1,000 Selectra™ chambers in the field
Slide 59: Applied's Growth in Process Control
Applied's Growth in Process Control $M Applied PDC revenue growth is 1,500 accelerating and outpacing the market 67% YoY eBeam inflection expands Applied’s 1,000 TAM 74% 12% CAGR eBeam Applied’s eBeam revenue nearly 63% Optical doubled in 2021 500 » VeritySEM for CD uniformity 52% » PROVision
Slide 60: Going Beyond Unit Process Tools to Deliver Solutions
Going Beyond Unit Process Tools to Deliver Solutions FASTER TIME TO MARKET, HIGHER VALUE, STICKIER UNIT PROCESS LEADERSHIP + BROADEST PORTFOLIO CO-OPTIMIZATION OF ~40% of our products PROCESSES / TOOLS now co-optimized INTEGRATED ~30% of our products MATERIALS now integrated SOLUTIONS ACTIONABLE INS
Slide 61: Inflections Over Time
Inflections Over Time LONGER TERM 3D DRAM Forksheet EMERGING CFET Gate-All-Around Backside Power Hybrid Bonding EXISTING EUV Enablement eBeam Metrology PERFORMANCE Wiring DRAM HKMG PPACt POWER AREA-COST * Partial list of key inflections Applied Materials External
Slide 62: Cl Maveniais.
Cl Maveniais. make possible