Microchip Technology Incorporated · NASDAQ:MCHP
Microchip Technology — Technical Presentation (May 2019)
26 slides from Microchip Technology's technical presentation, May 2, 2019
Slide 1: Getting Started With the PolarFire SoC FPGA
Getting Started With the PolarFire™ SoC FPGA Krishnakumar Ramamoorthi, Mi-V Ecosystem Manager Michael Gielda, Antmicro May 2, 2019
Slide 2: First Thursday's
First Thursday’s May 2 - Webinar 1: Discover Renode for PolarFire™ SoC Design and Debug June 6 - Webinar 2: How to Get Started with Renode for PolarFire SoC July 4 - Webinar 3: Learn to Debug a Bare-Metal PolarFire SoC Application with Renode Aug. 1 - Webinar 4: Tips and Tricks for Even Easier Polar
Slide 3: PolarFire SoC Introduction
PolarFire SoC Introduction Session 1: Discover Renode for Design and Debug
Slide 4: Enabling Purpose-Built, Real-Time Low Power Systems
Enabling Purpose-Built, Real-Time Low Power Systems Safety Critical Systems Imaging and Machine Collaborative Robots Learning Secure Communications and Smart Weapons, Industrial IoT Portable Embedded Systems Drones and UAVs 4
Slide 5: PolarFire SoC Summary
PolarFire SoC Summary ● Award Winning PolarFire FPGA Features ● 30 – 50 percent lower power ● Defense grade security ● Exceptional reliability ● Smallest form factors – 11x11, 16x16, 19x19 ● Hardened RISC-V Microprocessor Subsystem ● Linux® and real time in a deterministic, coherent CPU cluster ● 30
Slide 6: RISC-V Enabled Innovation Platform
RISC-V Enabled Innovation Platform ● Freedom to Innovate in: ● Linux and real-time ● Thermal and power constrained systems ● Securely connected IoT systems ● High-rel safety critical systems PolarFire SoC Architecture 6
Slide 7: Freedom to Start Software Development
Freedom to Start Software Development GDB Firmware Sample Catalog Projects Compiler Debugger Eclipse IDE Design Flow ● Free rapid software development and debug capabilities without hardware ● Complete PolarFire SoC processor subsystem model ● Available now 7
Slide 8: Introduction to Antmicro
Introduction to Antmicro ● Mi-V Ecosystem Partner ● Embedded systems design and creation ● Open source software, tools and hardware 8
Slide 9: Continuous Integration Based Development
Continuous Integration Based Development Renode - a new approach to complex embedded sy stems development
Slide 10: Renode
RINOD= & Py RISC-V'
Slide 11: Layer #3: Complex System
Layer #3 : Complex System Renode - a new approach to complex embedded sy stems development
Slide 12: Layer #2: The Device
Layer #2 : The Device Renode - a new approach to complex embedded sy stems development
Slide 13: Layer #1: System-on-Chip
Layer #1 : System - on- Chip Renode - a new approach to complex embedded sy stems development
Slide 14: PolarFire SoC FPGA Architecture
PolarFire SoC FPGA Architecture “Enabling the Freedom to Innovate” Renode - a new approach to complex embedded sy stems development
Slide 15: Previously - a USD 3000 development platform
Previously - a USD 3000 development platform Renode - a new approach to complex embedded sy stems development
Slide 16: Now - Renode, a free and open source framework
Now - Renode, a free and open source framework that’s in your PC (or server) Renode - a new approach to complex embedded sy stems development
Slide 17: Renode network analysis demo
Men a Renode ° x File Edit View Go Captur Statistics Q Analyze Source Destination 13:41 xcs 24.1211 0x66 [DEBUG] 8x4 Oxo Oxo client/radio OxO 0x40 OxAd Sending frane (2) ©x61 OxDC xB OxCD OxAB Ox1 OxO OxO Ox8 OxO Ox OxO Ox0 4 Frane 95: 45 bytes on w TEE 002.15.4 Data, Ost GLOMPAK @ (260 bits), 45 by
Slide 18: Zephyr HTTP Server demo
8740316059 Zephyr HTTP Server - Mozilla Firefox - 8 « Zephyr HTTP Serves x + € © 1920.22 retf OO = It Works! R=ZNOD= Temperature: 37.000 ‘OII7 [DEBUG] spil: SST enabled 0117 [DEBUG] spil rnet: Write to @xIF, bank @, value 0x5. 0119 [DEBUG] spil: SSI disabled 0120 [DEBUG] spil 0121 [DEBUG] spil.ether
Slide 19: PFSoC Support Highlights
PFSoC Support Highlights ● Interfaces for connection with multiple external elements ● Helps explore the flexibility of Renode Renode - a new approach to complex embedded sy stems development
Slide 20: SoftConsole Integration
SoftConsole Integration ● Standard IDE, comes bundled ● Linux and Windows® ● Examine the entire system as you’re developing code ● New and exciting abilities Renode - a new approach to complex embedded sy stems development
Slide 21: SoftConsole Integration
SoftConsole Integration ● Renode is extremely extendible ● Debug, tracing, visualization - we have all the data Renode - a new approach to complex embedded sy stems development
Slide 22: Automated testing with Renode
Execute 1 0 Command 9 ‘Test If vart Is Idle u 17 Should Generate Interrupts Create Machine Create Terminal Tester Start Emulation wait For wait For Line on vart Line on vart vart Is Idle Execute Command Wait For Line On art Execute Command Wait For Line On vart antmicro@renode-delt Preparing suites
Slide 23: Renode - Verilator integration
Dawid-Antmicro: ~/Documents/test/renode-ha/renode Byer - Verilator integration cpu: CPU.RtscV32 @ sysbus = cpuType: "rv329” privilegeArchitecture: PrivilegeArchitecture.Privi_09 clint: clint [e-3] -> cpu@[s-11] © priorittesEnabled : false // Power /Reset/Clock/Interrupt Bp clint: IRQControllers.Core
Slide 24: Renode - Verilator integration demo
Bgrode - Verilator integration as namie uartlite:sysbus.varto -.186@ Site! counter = 267 R=ZNOD= alive! counter alive! counter alive! counter alivet counter alive! counter alive! counter alive! counter alive! counter alive! counter alive! counter alive! counter = 261 alive! counter = 262 alive! coun
Slide 25: Summary
Summary • PolarFire SoC for purpose-built, real-time, low power systems • Get started today by downloading SoftConsole v6.0 • Use the Renode rapid development framework to build software including real, end-user applications • Visit www.microsemi.com/mi-v for complete Renode webinar series details,
Slide 26: Thank You
S MICROCHIP Thank You
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