Arteris, Inc. · NASDAQ:AIP
Arteris — Technical Presentation (December 2019)
18 slides from Arteris's technical presentation, Dec 3, 2019
Slide 1: Lessons Learned integrating AI/ML Accelerators into complex ISO 26262 Compliant Systems-on-Chip
Lessons Learned integrating AI/ML Accelerators into complex ISO 26262 Compliant Systems-on-Chip APPLICATION OF ISO 26262 FOR SEMICONDUCTORS 3 DECEMBER 2019, MUNICH KURT SHULER DIEGO BOTERO Vice President, Function Safety Engineer Functional Safety Manager Arteris IP Arteris IP
Slide 2: Arteris IP and ISO 26262
Arteris IP and ISO 26262 • ISO 26262 working group members and contributed to writing the 2nd Edition (2018) specification • Significant contributions to new Part 11, “Guidelines to application of ISO 26262 to semiconductors” 3 December 2019 Copyright © 2019 Arteris IP 2
Slide 3: Active Arteris IP Customers – Public
Active Arteris IP Customers – Public Transportation AI / Machine Learning IoT, Consumer Electronics & ASIC Very Large NXP Toshiba SoC Maker Major System OEM Japan System OEM #1 Toshiba Major ADAS System Maker Major FPGA Large Company Drone Maker Stealth AI Company Stealth AI Company Stealth AI Compa
Slide 4: The NoC interconnect is the SoC architecture
The NoC interconnect is the SoC architecture Arm® Cortex® CPU Subsystem Design-Specific Subsystems Machine Learning Subsystem Accelerator Subsystem(s) Application-specific IP Subsystem A76AE A76AE A76AE A76AE DSP IP IP Accel Accel Accel A76AE A76AE A76AE A76AE FlexNoC Interconnect DSU (L3 cache) DSU
Slide 5: NoC interconnect design
NoC component Hard IP NoC interconnect design • Complex circuit built of protocol converters, packetizers, switches, adapters. • Fills area between hard IPs • Balance between architectural specs (latency, QoS) and physical constraints • In NoC creation tools components are multi-variant parametrized
Slide 6: AI vs. “Regular” Chips
AI vs. “Regular” Chips Power Performance Area Safety Schedule 3 December 2019 Copyright © 2019 Arteris IP 6
Slide 7: Power
AI vs. Regular Chips Power • Accesses to off-chip DDR and HBM2 memories are huge power consumers – Mitigation: Use of on-chip memory schemes to maintain data on-chip and limit off-chip memory accesses • Larger chip area and with increased wire area proportion increases SoC-level power consumption –
Slide 8: Safety controller
Use existing interconnect and PMU features for power isolation IP SUBSYSTEMS MAY ALSO REQUIRE LBIST CONTROLLER AND WATCHDOG TIMER Safety island Arm Ethos- Cortex-R52 N77 NPU Audio Display Mali C71 FAULT Socket power SoC disconnect PMU Safety controller NoC power controller Mem Ctrl SRAM ROM/Flash UA
Slide 9: Performance
AI vs. Regular Chips Performance • High Bandwidth – Some industry-standard protocols like Arm AMBA AXI do not yet support more than 1024-bit wide interfaces • AI architectures require from 512-bit to 8K bit wide • Mitigation: Many teams rely on internal / modified solutions rather than industry-stan
Slide 10: Area
AI vs. Regular Chips Area • 7nm and smaller technology CD2_Clk processes increase SER CD1 CD2 • Long distances à Floorplan obstruction and clock tree distribution issues – Virtual channels SW SW – Source-synchronous communications • Mesh and ring topologies Source synchronous pipeline for distance a
Slide 11: Early physical prediction helps future layout
AI vs. Regular Chips Early physical prediction helps future layout Is target latency of 6 clock cycles between initiator and target achievable? clk domain B – 1.0 GHz clk domain A – 1.6GHz Put switch in clock domain A or B? Where should I Will 512-bit wire bundle Can 5x5 switch operate at place regi
Slide 12: Safety
AI vs. Regular Chips Safety • Safety and Reliability affected by lots of on-chip RAM – ECC checking • Timing critical paths and timing closure issues • Complex verification • Common issues: – More safety mechanisms can add more safety risk – Need industry-standard Work Product definitions: FMEDA, DF
Slide 13: Safety - Fault Injection
AI vs. Regular Chips Safety - Fault Injection • Fault Injection for large chips can be ETERNAL • Formal being integrated into fault simulators • Define Fault Injection strategy – Understand your item and vulnerabilities – Use of Directed & Random tests • Functional coverage • Use sampling capabiliti
Slide 14: Safety – RTL Fault Injection
AI vs. Regular Chips Safety – RTL Fault Injection Part 11 is your friend! ISO/FDIS 26262-11:2018 • RTL simulation is often the only practical method for … analysis of large chips – Faster (months vs. eons…) … – Fewer licenses – Easier to find root causes of issues and debug – Use proper stimuli (clo
Slide 15: Schedule
AI vs. Regular Chips Schedule • FuSa experts need to be involved at BEGINNING of SoC design – If you get involved after RTL freeze, you are wrong! • Read and follow the Assumptions of Use (AoU) for all your IP – Can be impossible to make changes late in schedule – Can be difficult (and expensive!) t
Slide 16: How Arteris IP can help you with AI Automotive SoCs
How Arteris IP can help you with AI Automotive SoCs • World-class knowledge of SoC architecture and interconnect implementation best practices – Broadcast and Multicast – Integrating caches and internal memories – AI SoC topologies: Meshes, rings, arbitrary trees, etc. • Integrating AI subsystems, s
Slide 17: Key Points / Next Actions for Functional Safety Teams
Key Points / Next Actions for Functional Safety Teams FuSa must be involved in at BEGINNING of SoC design schedule! #1 • Follow Assumptions of Use (AoU) • Perform analysis early enough to help architecture and implementation Use RTL fault injection for large designs #2 • Always consider your stimuli
Slide 18: Thank You!
Thank You! [email protected] [email protected]