ASML Holding NV · EURONEXT:ASML
ASML Holding NV — Investor Day (September 2021)
42 slides from ASML Holding NV's investor day presentation, Sep 29, 2021
Slide 1: Technology Strategy to Drive Moore's Law into Next Decade
Technology Strategy to Drive Moore’s Law into Next Decade Martin van den Brink President and Chief Technology Officer Public
Slide 2: Technology strategy: Key messages
Technology strategy • Holistic Lithography roadmap is driven by our unique Key messages patterning control solutions that deliver customer value via Slide 2 29 Sept. 2021 improved on product performance. • Moore’s Law is alive and well! Industry innovation • ASML’s comprehensive product portfolio is
Slide 3: Moore's Law evolution and customer roadmap; ASML's strategic priorities
• Moore’s Law evolution and customer roadmap ASML’s strategic priorities Public
Slide 4: Significant device innovation in logic ahead of us
Significant device innovation in logic ahead of us scaling roadmap continues to 1 nm and beyond Slide 4 29 Sept. 2021 3 nm 2 nm 1,5 nm 1 nm and beyond PP: 44-48, MP: 21-24 PP: 40-44, MP: 18-21 PP: 40-44, MP: 18-21 PP: 38-42, MP: 15-18 BPR BPR FinFET Nanosheets, BPR Forksheets, VHV std cell arch. CFE
Slide 5: Innovation is not limited to device level
Innovation is not limited to device level TSMC’s system roadmap to >300 B transistors Slide 5 29 Sept. 2021 WoW: Wafer on Wafer CoWoS: Chip on Wafer on Substrate HBM: 3D High Speed Memory RDL: Re Distribution Layer SOC: System on Chip CoW: Chip on Wafer FPGA: Field Programmable Grid Array InFo: Inte
Slide 6: Innovation is not limited to device level
Innovation is not limited to device level TSMC’s system roadmap to >300 B transistors Slide 6 29 Sept. 2021 WoW: Wafer on Wafer CoWoS: Chip on Wafer on Substrate HBM: 3D High Speed Memory RDL: Re Distribution Layer SOC: System on Chip CoW: Chip on Wafer FPGA: Field Programmable Grid Array InFo: Inte
Slide 7: Moore's Law evolution: the next decade
Moore’s Law evolution: the next decade Traditional scaling metrics like clock frequency have been saturated since 2005 Slide 7 29 Sept. 2021 Public data Customer Speculation 1020 projection Dennard Post Dennard 1018 scaling scaling 1016 1014 1012 1010 108 106 104 Clock Frequency1 [MHz] 102 1 1970 19
Slide 8: Moore's Law evolution: the next decade
Moore’s Law evolution: the next decade Scaling metric of transistor and litho density continues in this decade Slide 8 29 Sept. 2021 Public data Customer Speculation 1020 projection Dennard Post Dennard 1018 scaling scaling 1016 1014 1012 1010 Transistor density2 [#/mm2] 108 Device and layout optimi
Slide 9: Moore's Law evolution: the next decade
Moore’s Law evolution: the next decade A system metric measuring energy and time efficiency combined Slide 9 29 Sept. 2021 Public data Customer Speculation 1020 projection • Energy-Efficient Performance for systems and devices defined as Dennard Post Dennard 1018 scaling scaling 1016 [1/J.s] 1014 •
Slide 10: Moore's law evolution: the next decade
Moore’s law evolution: the next decade Device Energy Efficient Performance growth been saturated since 2005 Slide 10 29 Sept. 2021 Public data Customer Speculation 1020 projection Dennard Post Dennard System Energy scaling Efficient Performance3 1018 scaling [1/J.s] 1016 From transistor to system sc
Slide 11: Moore's Law evolution: the next decade
Moore’s Law evolution: the next decade System Energy Efficient Performance growth 3x/2yrs continues to 2040 Slide 11 29 Sept. 2021 Public data Customer Speculation 1020 projection System improvements System 1018 dominated by Transistor scaling scaling 1016 1014 Transistor Energy Efficient Performanc
Slide 12: Moore's law evolution: the next decade
Moore’s law evolution: the next decade From cost per transistor through density, to cost of time and energy through systems Slide 12 29 Sept. 2021 Public data Customer Speculation 1020 projection Dennard Post Dennard System Energy scaling scaling Efficient Performance3 1018 [1/J.s] 1016 From transis
Slide 13: Moore's law evolution: the next decade
Moore’s law evolution: the next decade System scaling to satisfy the need for performance and energy consumption Slide 13 29 Sept. 2021 1020 System improvements System Energy System Efficient Performance3 1018 dominated by Transistor scaling scaling [1/J.s] 1016 From transistor to system scaling 101
Slide 14: AMD 3D chiplet gives an 3.1-3.8 EEP improvement
AMD 3D chiplet gives an 3.1-3.8 EEP improvement By integrating memory with the processor in one package Slide 14 29 Sept. 2021 3x power reduction, Structural silicon 4-25% speed improvement 64MB L3 cache die Direct copper-to-copper bond Through Silicon Vias (TSVs) for silicon-to-silicon communicatio
Slide 15: Moore's law evolution: the next decade
Moore’s law evolution: the next decade System scaling to satisfy the need for performance and energy consumption Slide 15 29 Sept. 2021 Public data Customer Speculation 1020 projection System improvements System Energy System Efficient Performance3 1018 dominated by Transistor scaling scaling [1/J.s
Slide 16: Litho density scaling continues in this decade
Litho density scaling continues in this decade Overlay and Optical Proximity Correction errors shrink aggressively Slide 16 29 Sept. 2021 2x every 6 years Source: Average customer roadmap extended by ASML extrapolation May 2021, averaged with 2020 IRDS Roadmap Mustafa Badaroglu, “IRDS IFT – More Moo
Slide 17: Memory roadmap for the next decade
Memory roadmap for the next decade DRAM scaling below 10 nm and NAND stacking continues > 600 layers Slide 17 29 Sept. 2021 DRAM After 10 years Now Challenge < 10 nm 1y 1z 1a 1b 1c 1d 0a NAND After 10 years Now Challenge > 600 layers 96 128 176 2xx 3xx 4xx 5xx 6xx Source: Sk hynix, S.H.Lee, "Memory'
Slide 18: Projection of lithography layers by technology
Projection of lithography layers by technology Slide 18 29 Sept. 2021 KrF Logic Layer stack 5 nm 3 nm 2 nm ~1.5 nm 1 nm DRAM KrF EUV – High-NA Layer stack EUV 1A 1B 1C 0A 0B ArFi ArF KrF KrF I-Line 3D-NAND Layer stack 176L 2xxL 3xxL 4xxL 5xxL 2021 ~2030 Source: ASML Corporate Strategy and Marketing
Slide 19: Projection of lithography layers by technology
Projection of lithography layers by technology Lithography layer count grows, driven by DUV and EUV Slide 19 29 Sept. 2021 KrF Logic Layer stack 5 nm 3 nm 2 nm ~1.5 nm 1 nm DRAM KrF EUV – High-NA Layer stack EUV 1A 1B 1C 0A 0B DUV KrF 3D-NAND Layer stack 176L 2xxL 3xxL 4xxL 5xxL 2021 ~2030 Source: A
Slide 20: Semiconductor and shrink roadmap: the next decades
Semiconductor and shrink roadmap: the next decades Slide 20 29 Sept. 2021 10⁵ In the next decade, system scaling continues to fuel the need of advanced semiconductor solutions where litho shrink Relative manufacturing cost per component 1962 10⁴ remains key to improving circuit density and cost. 196
Slide 21: Moore's Law evolution and customer roadmap; ASML's strategic priorities
Moore’s Law evolution and customer roadmap • ASML’s strategic priorities Public
Slide 22: ASML's strategic priorities
ASML’s strategic priorities Slide 22 29 Sept. 2021 Strengthen ▪ Enhance execution capabilities to deliver performance, cost customer trust and robustness to customers needs Holistic litho and applications ▪ Build a leading position in edge placement error DUV competitiveness ▪ Drive DUV performance
Slide 23: Our holistic portfolio is more important than ever
Our holistic portfolio is more important than ever Slide 23 Lithography scanner with 29 Sept. 2021 advanced control capability EUV: NXE platform DUV: XT and NXT Etch and platform deposition tools Process window Process window Prediction and Control Enhancement Optical proximity correction YieldStar
Slide 24: Applications
Our holistic portfolio is more important than ever Slide 24 29 Sept. 2021 EUV DUV High-NA Applications Public
Slide 25: Applications: strategic directions
APPS Applications: strategic directions Deliver leading solutions for optical and e-beam metrology and inspection Slide 25 29 Sept. 2021 Customer Value ASML Apps product roadmap Capturing more wafer signatures to • Productivity improve robust on-wafer process control • Robust alignment schemes Nanom
Slide 26: E-beam inspection has inherent resolution advantage
APPS E-beam inspection has inherent resolution advantage Increasing throughput through increasing parallelism with multibeam Slide 26 29 Sept. 2021 1000000 Min defect size for 2 nm node and below 100000 Optical Bright Field Inspection 10000 1000 Gen 3 Multibeam (~2028) Throughput [mm²/hr] Increased
Slide 27: Metrology, Inspection & Patterning Control Roadmap
APPS Metrology, Inspection & Patterning Control Roadmap Slide 27 29 Sept. 2021 Platform Application 2020 2021 2022 2023 2024 ≥ 2025 Scanner Interfaces Scanner Increasing Scanner Actuation (DUV and EUV), EPE Control and Control Software(Overlay Optimizer) Control (Imaging Optimizer) Overlay Metrology
Slide 28: NXT:2050i in volume manufacturing at customers
DUV NXT:2050i in volume manufacturing at customers 20% overlay improvement, faster reliability and productivity ramp-up Slide 28 29 Sept. 2021 NXT:2050i Matched machine Dedicated chuck overlay ~1.2 nm overlay ~0.8 nm 6000 5,000 wafers per day in 18 days 200 180 hours reliability in 13 weeks 180 5000
Slide 29: DUV: Strategic directions
DUV DUV: Strategic directions Deliver leading solutions for advanced capabilities and higher productivity Slide 29 29 Sept. 2021 Customer value ASML DUV product roadmap Overlay Improve overlay (stability) especially • NXT:2100i with optics and alignment improvements for matching to EUV More good waf
Slide 30: DUV product portfolio to support all market segments
DUV DUV product portfolio to support all market segments Slide 30 29 Sept. 2021 Wavelength NA, Half pitch 2020 2021 2022 2023 2024 2025 NXT:2000i NXT:2050i NXT:2100i NEXT Continue critical innovation on advanced NXT platform for improved imaging, overlay and productivity 2.0 nm | 275wph 1.5 nm | 295
Slide 31: EUV 0.33 NA adoption enabled by platform maturity
EUV EUV 0.33 NA adoption enabled by platform maturity in high-volume manufacturing Slide 31 29 Sept. 2021 100% 3000 System output Max wafers per day (single system, weekly average) 95% 2500 90% Installed base system availability Wafers per day Availability 4 weeks moving average (end of period) 85%
Slide 32: EUV: strategic directions
EUV EUV: strategic directions Enabling cost-efficient scaling for advanced nodes Slide 32 29 Sept. 2021 Customer value using EUV ASML EUV product improvements Better device performance: simpler • Technology roadmap: per node (resolution), improve design and superior electrical imaging, overlay and d
Slide 33: High-NA to prevent cycle time and process complexity increase
EUV High-NA to prevent cycle time and process complexity increase like low NA did for immersion Slide 33 29 Sept. 2021 0.55-NA EUV preferred 0.33-NA EUV Insertion 5 mask steps, cycletime (product dependent) 3 process complexity (a.u.) DUV EUV- 0.33NA EUV- 0.55NA 3 0.33-NA insertion supports single H
Slide 34: High-NA EUV: strategic directions
EUV High-NA EUV: strategic directions Enabling cost-efficient scaling for next generation advanced nodes Slide 34 29 Sept. 2021 Customer value High-NA EUV ASML High-NA EUV product improvements 0.55 NA enables 1.7x smaller features and 2.9x increased density • Technology roadmap: per node (resolution
Slide 35: High-NA EUV is in the realization phase
EUV High-NA EUV is in the realization phase On multiple ASML and supplier locations Slide 35 29 Sept. 2021 Oberkochen, Germany optics system manufacturing facilities Veldhoven, the Netherlands, system bottom test EUV 0.55 NA optics Toulon, France, Frame milling Wilton, USA, system top test Public
Slide 36: EUV 0.55 NA expected to be added to portfolio in 2025-2026
EUV EUV 0.55 NA is expected to be added to EUV portfolio for high volume in 2025 - 2026 while continue improving the 0.33 NA platform Slide 36 29 Sept. 2021 Wavelength NA, Half pitch 2020 2021 2022 2023 2024 ≥2025 NXE:3400C NXE:3600D 0.33NA continuous imaging, NXE:3800E in line overlay and productiv
Slide 37: TRUST: Commonality across EUV, DUV & High-NA platforms
TRUST Commonality across EUV, DUV & High-NA platforms Allows faster and more cost-effective innovation, production and maintenance Slide 37 29 Sept. 2021 DUV EUV Alignment Sensor Level sensor Common Technology Metrology used in both Wafer handling DUV & EUV platform NXT (248nm dry) NXT (193 nm dry)
Slide 38: TRUST: Maximizing customers' good wafers per day
TRUST Maximizing customers’ good wafers per day Next to minimizing system down time Slide 38 29 Sept. 2021 100% 100% 100% System downtime System downtime serving according to customer needs standardized Process-specific inefficiencies definition >97% e.g., system down to meet customer specs, layer q
Slide 39: TRUST: EUV is the most energy efficient solution
TRUST EUV is the most energy efficient solution We expect net energy savings of more than 45% over alternative processes Slide 39 29 Sept. 2021 EUV 0.55 EUV 0.33 Electrical power reduction Electrical power reduction Immersion to EUV 0.33 productivity [wph] EUV 0.33 to EUV 0.55 at 220 wph Side wall A
Slide 40: Technology strategy: Key messages
Technology strategy • Holistic Lithography roadmap is driven by our unique Key messages patterning control solutions that deliver customer value via Slide 40 29 Sept. 2021 improved on product performance. • Moore’s Law is alive and well! Industry innovation • ASML’s comprehensive product portfolio i
Slide 41: Forward Looking Statements
Forward Looking Statements Slide 41 29 Sept. 2021 This presentation contains statements that are forward-looking, including statements with respect to expected industry and business environment trends including expected growth, outlook and expected financial results, including expected net sales, gr
Slide 42: Investor Day Virtual
Investor Day Virtual