Synopsys, Inc. · NASDAQ:SNPS
Synopsys — Technical Presentation (2021)
17 slides from Synopsys's technical presentation, 2021
Slide 1: Full-Chip CDM Analysis: Is Static Simulation Enough?
2020 International ESD Workshop Full-Chip CDM Analysis: Is Static Simulation Enough? Jordan Davis, Samsung Electronics Yuri Feinburg, Silicon Frontline Chanhee Jeon, Samsung Electronics Simon Young, Silicon Frontline Sung-Jun Song, Samsung Electronics [email protected]
Slide 2: Objective and Significance
Objective and Significance Due to complexity and cost of developing today’s integrated circuits, it has become increasingly important to perform full chip simulations to find ESD weak points. In this poster, charged device model (CDM) simulations are reviewed. Such CDM events are characterized by fa
Slide 3: Biography
Biography ■ Career ─ ON Semi - ESD design intern, March 2008 ─ ON Semi - ESD discrete device & process designer, 2009 - 2017 ─ Samsung Electronics - Full chip ESD verification, 2017 - present ■ Education ─ B.S.E in electrical engineering in 2009, Arizona State University ─ M.S.E in electrical engine
Slide 4: Device Behavior: ESD Snapback Devices
Static Device Behavior ■ Determining static device behavior for ESD snapback devices: 100ns 1ns 2.5 8.75 7. Slope = 2.4 1.875 Slope = 2.0 Ron = 0.42Ω Current (A) Current (A) Ron = 0.50Ω 5.25 Von = 3.7V 1.25 Von = V4.0 3.5 0.625 1.75 0. 0. 0. 2. 4. 6. 8. 0. 1.75 3.5 5.25 7. Voltage (V) Voltage (V) ■
Slide 5: Device Behavior: ESD Diodes
Static Device Behavior ■ Determining static device behavior for ESD Diodes: 100ns 7.5 6. 4.5 Current (A) 3. 1.5 0. 0. 1. 2. 3. 4. Voltage (V) ■ 100ns diode varying slope is problematic for choosing Ron and Von ─ Pseudo-linear region can be chosen, but which one 2019 International ESD Workshop 5
Slide 6: Device Behavior: ESD Diodes 1ns
Static Device Behavior ■ Determining static device behavior for ESD Diodes: 1ns 1ns 18. 8. Slope = 3.3 13.5 6. Ron = 0.30Ω Von = 1.5V Current (A) Current (A) 9. CDM Region 4. 4.5 2. 0. 0. 0. 2. 4. 6. 8. 1.5 2.125 2.75 3.375 4. Voltage (V) Voltage (V) ■ Current range for 250V and 500V CDM provides a
Slide 7: Static Versus Dynamic
Static Versus Dynamic ■ Difference in peak current and propagated voltage ■ Static simulation creates higher stress condition Static VDD Dynamic VDD 12A 12A Pad Pad Connection Connection Parasitic Parasitic VSS VSS
Slide 8: Static Vs. Dynamic
Static Vs. Dynamic ■ Two examples where static analysis is pessimistic Large coupling to GND (from G VDD or ESD net) S V V V V VDD VDD VG VG GND t GND t VS t VS t Dynamic Static Dynamic Static (exaggerated) ■ Static delta-V > dynamic delta-V ■ Static delta-V > dynamic delta-V
Slide 9: Transient ESD Device Behavior
Transient ESD Device Behavior ■ Turn-On latency Net charged during I I I CDM event Static t t t A Clamps share B Electrically A C B ‘close’ ICDM equally clamp I I I C Electrically Dynamic DOES NOT CONDUCT ‘distant’ Local env. t t t clamp determines if A C B clamp turns on ■ Here, ESRA models pseudo-
Slide 10: Bond Wire Inductance
Bond Wire Inductance I/O circuits Analog domains Global supplies Package Package-contained net R included Bond-wire related L effect included BGA Wire bond example
Slide 11: Bond Wire Inductance Approximation
Bond Wire Inductance Approximation ■ Calculated resistance value can compensate for bond wire inductance in static simulation. ■ CDM peak pulse duration can be used for frequency. 𝜇 2𝑙 ! L= ∗ l 𝑙𝑛 − 0.75 2𝜋 𝑟 Device Input CDM Waveform Resistance 5 25 4 20 3 𝑅" = 2𝜋𝑓𝐿 0.5ns 15 2 Ω 0.5 ns…
Slide 12: Static Simulation Analysis
Static Simulation Analysis ■ Static simulation results IO 1 IO 2 IO 3 IO Cells IO 1 IO 2 IO 3
Slide 13: Failure Analysis Results for the same case
Failure Analysis Results for the same case Simulation Vs. Failure Analysis
Slide 14: Other Transient ESD Device Behaviors
Other Transient ESD Device Behaviors ■ Voltage overshoot is not captured in static simulation ─ In static simulation: ─ All devices have constant resistance ─ Devices are on or off with no transition state Diode forward and reverse recovery p+ n— STI ■ CMOS Diode Analysis Forward bias e injection ■
Slide 15: Additional Transient-Related Discussion Points
Additional Transient-Related Discussion Points ■ Specific transient related behaviors ─ Diode and GGNMOS Gate protection ─ Switching FETs ─ Inter-rail parasitic capacitance ─ Package location of pulse ─ Integrated vs. peak power 2019 International ESD Workshop 15
Slide 16: Conclusion
Conclusion ■ In advanced nodes with ICs that have billions of devices, dynamic simulations are a computational impossibility. ■ Static simulations can take into account transient effects through approximations ■ Static simulation produces a higher stress scenario that dynamic. ■ Not all transient ef
Slide 17: Acknowledgements
Acknowledgements ■ Thank you to the many people