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ARM — European Processor Initiative — Technical Presentation (September 2019)

14 slides from ARM's technical presentation, September 2019

  1. Slide 1: FFTW3: Leveraging the Scalable Vector Extension (SVE)

    FFTW3: LEVERAGING THE SCALABLE VECTOR EXTENSION (SVE) SEPTEMBER 2019 European Processor epi Initiative

  2. Slide 2: Framework Partnership Agreement in European Low-Power Microprocessor Technologies

    European Processor Initiative epi FRAMEWORK PARTNERSHIP AGREEMENT IN EUROPEAN LOW-POWER MICROPROCESSOR TECHNOLOGIES THIS PROJECT HAS RECEIVED FUNDING FROM THE EUROPEAN UNION’S HORIZON 2020 RESEARCH AND INNOVATION PROGRAMME UNDER GRANT AGREEMENT NO 826647 Copyright © European Processor Initiative 201

  3. Slide 3: Fastest Fourier Transform in the West

    Initiative “FASTEST FOURIER TRANSFORM IN THE WEST” = FFTW, “Fastest Fourier Transform in the West”, is a library implementing Fourier Transform and approximations thereof and self-adapt to the hardware = It has been around for over two decades = Widely in use in the HPC community = Intel’s MKL inclu

  4. Slide 4: References: The Design and Implementation of FFTW3

       [1] M. Frigo and S. G. Johnson, "The Design and Implementation of  FFTW3," in Proceedings of the IEEE, vol. 93, no. 2, pp. 216-231, Feb. 2005. doi: 10.1109/JPROC.2004.840301

  5. Slide 5: SIMD Codelets

    European Processor Initiative SIMD CODELETS = “genfft” uses multiple algorithms to generate “codelets” = Small full FFTs, Cooley-Tukey, Bluestein, Rader, ... = It can generate multiple variants for a single size of a single algorithm = e.g. favoring Fused-Multiply-Add (FMA) or not, etc. One possible

  6. Slide 6: AVX-512

    AVX-512 /* SIMD complex vector length – FP64, FP32 */  #define VL DS(4, 8) /* permute the Real and Imaginary part of each complex */ #define FLIP_RI(x) SUFF(_mm512_shuffle)(x, x, DS(0x55,0xB1))  /* element-wise FMA */ #define VFMA(a, b, c) SUFF(_mm512_fmadd)(a,  b, c) /* similar, with a == ‘i’ */

  7. Slide 7: FFTW3 codelet generator

    FFTW3 codelet generator  SVE SIMD C codelet implementation  with SIMD header file macros  C codelets SVE codelets  FFTW3 base library  High- performance dynamic FFT implementation

  8. Slide 8: Using SVE for FFTW3 SIMD

    Initiative USING SVE FOR FFTW3 SIMD = SVE has one specificity not in SSE, AVX, == SVE includes specific instructions to AltiVec, ... : itis scalable support complex arithmetic, the basis for = That means, the vector width is not FFTW3's computations known at compile time — it can be = |tshould help

  9. Slide 9: SVE

    SVE /* FIXME: this hardwire to 512 bits */ #define VL DS(4, 8)  /* permute the Real and Imaginary part of each complex */ #define FLIP_RI(x) TYPE(svtrn1)(TYPE(svtrn2)(x,x),x) /* element-wise FMA */  #define VFMA(a, b, c) TYPESUF(svmad,_z)(ALLA,b,a,c) /* similar, with a == ‘i’ */ #define VFMAI(b, c

  10. Slide 10: GitHub arm-sve repository

              https://github.com/rdolbeau/fftw3/tree/arm-sve

  11. Slide 11: SVE, masked

    SVE, masked /* FIXME: this hardwire to 512 bits */ #define VL DS(4, 8)  /* permute the Real and Imaginary part of each complex */ #define FLIP_RI(x) TYPE(svtrn1)(TYPE(svtrn2)(x,x),x) /* element-wise FMA */ #define VFMA(a, b, c)  TYPESUF(svmad,_z)(MASKA,b,a,c) /* similar, with a == ‘i’ */ #define V

  12. Slide 12: GitHub arm-sve-alt repository

             https://github.com/rdolbeau/fftw3/tree/arm-sve-alt

  13. Slide 13: SUPERCOP benchmark link

      ☺      https://bench.cr.yp.to/supercop.html crypto_stream/chacha20/dolbeau/arm-sve

  14. Slide 14: EPI Partners

    Initiative EPI PARTNERS MW, @ ere: AOS datinen EGE @) KaLray 4 soucr Gemidynamic ise Z Z Fraunhofer Forschungszontrum tconcgn ad ITwM &y E4 CINECA cea errs) — FS 3 COMPUTER CHALMERS: UNIVERSITA DI PISA ENGINEERING INSTITUTE OF COMPUTER SCIENCE MIT QB emmaricr antl ky &<raee. E an Processor Initiativ

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