Asml Holding Nv · EURONEXT:ASML

Asml Holding Nv — Investor Day (November 2014)

32 slides from Asml Holding Nv's investor day presentation, Nov 24, 2014

1. Slide 1: Market Update

   Market Update Peter Jenkins Vice President, Marketing 24 November 2014

2. Slide 2: Forward looking statements

   Forward looking statements Public Slide 2 This document contains statements relating to certain projections and business trends that are forward-looking, including statements with respect to our November 2014 outlook, expected customer demand in specified market segments, expected sales levels and t

3. Slide 3: Outline

   Public Slide 3 November 2014 Outline • Introduction • ASML value drivers • Market opportunity & affordability

4. Slide 4: Some people are predicting the imminent end of Moore's law

   Some people are predicting the imminent end of Moore’s law Public Slide 4 November 2014

5. Slide 5: There is a rich pipeline of new scalable memory devices coming to market

   There is a rich pipeline of new scalable memory devices Public coming to market Slide 5 November 2014

6. Slide 6: Plenty of ideas and competition on how to continue to shrink Logic

   and plenty of ideas & competition on how to continue Public to shrink Logic Slide 6 November 2014

7. Slide 7: Customer Shrink Roadmap

   Customer Shrink Roadmap Public Slide 7 November 2014 HVM 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 Poly SiON HiK Metal Gate FinFET III-V/Ge channel ? Gate All Around ? Logic 28nm 20nm 14/16nm 10nm 7nm 5nm 3nm DRAM Working Memory 3xL 2xH 2xM 2xL 1xH 1xM 1xL MRAM 1xH 1xM 1xL Planar Floati

8. Slide 8: Process evolution essential to enable increasing processing and graphics capabilities of mobile devices

   Process evolution essential to enable increasing processing & graphics capabilities of mobile devices Public Slide 8 November 2014 Shrink : Integrate functions, increase processor & memory capacity, improve speed & power efficiency, lower cost 65nm 45nm 32nm 28nm 22nm 20nm 14nm Add functions, increa

9. Slide 9: Process evolution essential to enable increasing processing and graphics capabilities of mobile devices

   Process evolution essential to enable increasing processing & graphics capabilities of mobile devices Public Slide 9 November 2014 Shrink : Integrate functions, increase processor & memory capacity, improve speed & power efficiency, lower cost 65nm 45nm 32nm 28nm 22nm 20nm 14nm Add functions, increa

10. Slide 10: Enabling an ecosystem with considerable financial means and strong incentives to drive innovation

    Enabling an ecosystem that has considerable financial means and strong incentives to drive innovation … Public Slide 10 November 2014 Leading technology companies in the semiconductor industry ecosystem (EBIT 2013, B$) ASML (2) AMAT (1) TEL (1) Semi equipment TSMC (7) Semi manufacturers (13) TI (3)

11. Slide 11: Outline

    Public Slide 11 November 2014 Outline • Introduction • ASML value drivers • Market opportunity & affordability

12. Slide 12: EUV Value Driver: ~5x Resolution Enhancement

    EUV Value Driver : 3 ~ 5x Resolution Enhancement Public Slide 12 ArF immersion EUV November 2014 k1 difficulty, l l limit = 0.25 Resolution = k1 x NA k1 = 0.265 k1 = 0.32 strong OPC mask OPC mask l Wavelength 193nm 13.5nm NA Numerical NA 1.35 NA 0.33 NA > 0.5 Aperture Maximum Current Future Resoluti

13. Slide 13: There are multiple roads to shrink

    There are multiple roads to shrink Public Slide 13 2D Multi Patterning or EUV 1D Self Aligned Multiple November 2014 single expose Patterning (SAMP) LELE (or EUV SE) LELELE (or EUV SE) SADP (D=Double) SAQP (Q=Quadruple) LE #1 LE #1 Mandrel Mandrel Process Flow Spacer Spacer #1 LE #2 LE #2 Spacer cut

14. Slide 14: EUV process simplification example

    EUV process simplification example : Public 2D Logic Metal Interconnect illustration Slide 14 November 2014 EUV Single patterning ArFi LE4 Patterning ArFi SAQP # Steps Mask 1 4 1 2 3 66 1 2 3 4 5 Etch 1 4 1 2 3 j 97 1 2 3 4 5 6 9 8 Spacer 41 4 3 2

15. Slide 15: EUV Processing Cost per Layer saving

    EUV Processing Cost per Layer saving: 20% ~ 130% Public Slide 15 250% November 2014 130% 225% 200% 175% 20% Relative Cost Other 150% Patterning Cost 125% 100% 75% Litho OpEx 50% Litho CapEx 25% 0% EUV * ArFi LE4 ArFi SAQP * NXE:3350B, 95WPH, 30mJcm-2

16. Slide 16: EUV Resolution Benefits > Patterning Cost Reduction

    EUV Resolution Benefits > Patterning Cost Reduction Public Slide 16 November 2014 1 2D Patterning + 2 Process Simplification = 3 Lower Cost Shrink ~ 50% Δ More effective shrink Fewer process steps • Lower patterning cost • Smaller die due to reduced • Higher defect limited yield • Fewer process step

17. Slide 17: Customer roadmaps require continuous improvement in Overlay and Focus Performance

    Customer roadmaps require continuous improvement in Public Lithography Overlay and Focus Performance Slide 17 November 2014 ASML holistic roadmap delivers both scanner & process application improvements to secure low rework & high yield in volume manufacturing Overlay [nm] Focus [nm] 8 100 Customer

18. Slide 18: Overlay Value: ~€100M Cost Saving per Year for 100k WSpM

    Overlay Value: 1nm improvement @ 20nm Logic Node ~ €100M Cost Saving per Year for 100k WSpM Public Slide 18 November 2014 6nm Overlay 5nm Overlay Production 5nm Process Spec Cost Saving Rework limit Lot-Lot Statistical 14% Overlay Process Control < 1% rework rework 13% Rework ~ €33M / year ArFi Rewo

19. Slide 19: ASML platform approach enabling extendibility and upgradability

    ASML Platform approach enabling Extendibility & Upgradability has been an essential factor in ASML success in the Memory sector Public Slide 19 November 2014 Example : DRAM process migration from D2xM to D1xH 180% Apps 160% Relative Litho CapEx for 1k WSpM Dry Immersion ASML 140% CapEx Initial CapEx

20. Slide 20: Outline

    Public Slide 20 November 2014 Outline • Introduction • ASML value drivers • Market opportunity & affordability

21. Slide 21: NVM market transitions & ASML opportunities

    NVM market transitions & ASML opportunities Public 21 November 2014 1 2 3 4 5 1x x8 Planar 3D-new 2D3D 3D 2x x8 ReRAM ReRAM 5x ≥ x96 Today 3D-NAND 5x x48~x64 wafer volume 5x x32 5x x24 Challenges • Scaling @ <20 electrons with 3-bit/cell • <20nm patterning with SAQP 2xL 1xH 1xM Market 1xL : 1xVL •

22. Slide 22: NVM market transitions & ASML opportunities

    NVM market transitions & ASML opportunities Challenges : Public 22 • Memory hole patterning (CDU, elipticity, slope) November 2014 1 2 3 4 • Wafer stress,& 5  x8 scaling 32 1x >96 stacks • Fab conversion ReRAM cost & output loss  new fabs Planar 3D-new 2D3D 3D Market : ReRAM2x x8 • 256Gb  ≥1Tb d

23. Slide 23: NVM market transitions & ASML opportunities

    NVM market transitions & ASML opportunities Public 23 November 2014 1 2 3 4 5 1x x8 Planar 3D-new 2D3D 3D 2x x8 ReRAM ReRAM X-point / ReRAM challenges 5x ≥ x96 Today • Device type & material selection / properties • Scaling cell size / cost 3D-NAND 5x x48~x64 wafer volume Market • Initial as SCM 1~

24. Slide 24: Lithography market opportunity for Flash Memory

    Lithography market opportunity for Flash Memory Public EUV insertion for scaling Planar & 3D, ReRAM Slide 24 November 2014 Relative Exposure Passes Relative CapEx / 1k WSpM 175% 450% Dry Apps Immersion Process simplification 400% 150% opportunity with EUV EUV Dry 350% + 50% 125% Immersion with EUV 3

25. Slide 25: NAND bit cost scaling and customer transition estimates

    NAND bit cost scaling and customer transition estimates Public Slide 25 November 2014 1 1 3D-2D cost cross over 3D NAND transition 2 ReRAM introduction challenges • Capital expenditure to 2D Greenfield convert a fab from 2D NAND planar to 3D ~ 4x $/GB normal planar node 0.1 1 conversion 2 Depreciate

26. Slide 26: Logic market transitions & ASML opportunities

    Logic market transitions & ASML opportunities Public Slide 26 November 2014 1 2 3 4 Legacy for Image 28nm long lifetime Shrink  transistor Shrink  transistor? Sensors, IoT etc. for low cost Logic Fast ramps for mobile EUV insertion Today 7 nm wafer volume 10 nm 14/16 nm FinFET Challenges • Immersi

27. Slide 27: Logic market transitions & ASML opportunities

    Logic market transitions & ASML opportunities Public Slide 27 November 2014 1 2 3 4 Legacy for Image 28nm long lifetime Shrink  transistor Shrink  transistor? Sensors, IoT etc. for low cost Logic Fast ramps for mobile EUV insertion Challenges Today 7 nm • Transistor & material changes wafer volume

28. Slide 28: Logic market opportunity: increased passes with multiple patterning, higher Litho CapEx with EUV

    Logic market opportunity: increased # passes with Public Multiple-Patterning, higher Litho CapEx with EUV Slide 28 November 2014 Relative # Exposure Passes Relative CapEx / 1k WSpM 180% 275% Dry Apps 250% Dry 160% +30% NoN Immersion ArFi only EUV 225% Immersion + 35% ~ 50% NoN 140% EUV +10% NoN 200%

29. Slide 29: Logic Cost / Function returns to historical trends with EUV

    Logic Cost / Function returns to historical trends with EUV Litho CapEx share grows as multiple patterning costs reduced Public Slide 29 November 2014 Relative Cost per Wafer +17% NoN +4% NoN +44% 31% NoN 29% 1.00 20% Relative Cost per Function 18% 15% 16% 1.00 14% 12% -45% NoN 0.10 Litho Other Patt

30. Slide 30: External sources support the continued growth of Litho

    External sources support the continued growth of Litho Public Slide 30 November 2014 Historically Litho’s share of Independent research analysts the equipment market has grown expect Litho’s share in equipment Litho’s share of Wafer Equipment, to increase SEMI Litho’s share of Wafer Equipment spend,

31. Slide 31: Summary

    Summary Public Slide 31 November 2014 • Moore’s law continues • Strong technology pipeline & competition to continue scaling memory & logic • Supported by a large profit pool and incentive to make it happen • ASML delivers compelling Customer value • EUV - to enable continued cost effective shrink •

32. Slide 32: Public Slide 32 November 2014

    Public Slide 32 November 2014

ASML — Investor Day (November 2014) on 6ix