Asml Holding Nv · EURONEXT:ASML
Asml Holding Nv — ISS (Industry Strategy Symposium), Half Moon Bay 2007
49 slides from Asml Holding Nv's conference presentation, Feb 6, 2007
Slide 1: Shrink, an expanding (litho) market
Shrink, an expanding (litho) market Martin van den Brink Executive Vice President Marketing and Technology ISS, Half Moon Bay, Jan 9, 2007 Immersion EUV
Slide 2: Content
Content The demand for shrink continues Litho roadmap Litho integration Litho cost Summary
Slide 3: Shrink rates for Logic, DRAM, and NAND flash
Shrink rates for Logic, DRAM, and NAND flash Source: Various customers, dates determine production start/qualification Year Logic NAND DRAM
Slide 4: Shrink
Shrink Shrink speed is defined using “half pitch” Half pitch is led by Flash with k factors below 0.30 DRAM is trailing Flash by about 10% Logic and µ P are trailing Flash by about 50% Logic customers use “node” instead of “half pitch” On average, the relation is 70% “half pitch” = ”node”
Slide 5: IC characteristics & Lithography implications
IC characteristics & Lithography implications NAND Flash X-point storage transistor 4 F 2 1 4 1D Dense Resolution Strong 0.27 ~ 0.29 DRAM Transistor + Capacitor 6~8 F 2 1D & 2D Dense Imaging & overlay Moderate 0.29 ~ 0.31 Cell layout Logic / SRAM 6 Transistor (SRAM) 50~60 F 2 2D Random OPC, DoF Weak
Slide 6: Shrink drives cost per function and market growth
NAND size, GB NAND Revenue, M$ Projected cross- over HDD - NAND, GB Shrink drives cost per function and market growth Source: Gartner Dataquest, iSuppli, ASML 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 NAND cost, $ / GB 0.01 0.10 1.00 10.0 1,000 10,000 5,000 10,000 15,000 20,000 25,000 3
Slide 7: NAND Flash fastest growing IC segment between 2006 and 2009
Sources: ASML MCC, VLSI Research, iSuppli, SIA NAND Flash fastest growing IC segment between 2006 and 2009 in terms of silicon exposure area DRAM LOGIC NAND NOR ANALOG MICRO Other CAGR Exposure Area 06-09 [%] Segment size: 20 Bio. US$
Slide 8: Resolution, CD uniformity & overlay drive shrink
Node Aggressive Typical Relaxed 130 nm 90 nm 65 nm 45 nm 32 nm Resolution, CD uniformity & overlay drive shrink Layout 6 transistor SRAM Cell Design Rule & Cell Area [ m m 2 ] CD CD Spacing X-section through Cell Source: IMEC, TI 2.00 2.50 3.00 1.00 1.25 1.50 0.45 0.55 0.80 0.20 0.27 0.34 0.10 0.13
Slide 9: Overlay and resolution key for device scaling
Overlay and resolution (-control) key for device scaling Modeled equal 99.9% yield plane
Slide 10: Content
Content The demand for shrink continues Litho roadmap Dry Immersion Double patterning EUV Litho integration Litho cost Summary
Slide 11: Roadmap scenarios
100 65 45 32 22 16 11 year 2005 2007 2009 2011 2013 2015 half pitch Roadmap scenarios Resulting k 1 as function of resolution, wavelength and NA k 1 = (half pitch) * NA / wavelength Most aggressive k 1 in production today = 0.3, physical limit single exposure = 0.25 Practical limit double patterning
Slide 12: First super high NA immersion system enables 45 nm
First super high NA immersion system enables 45 nm 100 65 45 32 22 16 11 year 2005 2007 2009 2011 2013 2015 half pitch First super high NA immersion system enables 45 nm [nm] NA 0.80 0.32 0.93 0.31 1.20 0.40 0.28 1.35 0.31 0.22 0.15 1.55 0.26 0.18 13.5 0.25 0.59 0.41 0.35 0.57 0.41 0.45 0.53 0.37
Slide 13: Overview dense line 1700i imaging results
-300nm NF +300nm +450nm -500nm -180nm +180nm 950nm DoF -240nm NF +120nm +210nm -300nm -120nm +60nm 500nm DoF -150nm NF +150nm +210nm -210nm -90nm +90nm 400nm DoF 50nm 1.2NA, =0.74/0.94, annular, XY polarization, k1 = 0.31 45nm 1.2NA, =0.82/0.97, C-Quad-30, XY polarization, k1 = 0.28 42nm 1.2NA, =0.8
Slide 14: Immersion performance deficiency not impacting yield
Immersion performance deficiency not impacting yield Teruhiko Kodama, NEC, Symposium on Immersion Technology, Kyoto, oct 06
Slide 15: Roadmap scenarios, the impact of immersion
Max NA water-based 193 nm immersion requires double patterning to get to 32 nm 100 65 45 32 22 16 11 year 2005 2007 2009 2011 2013 2015 half pitch Roadmap scenarios, the impact of immersion Water-based 193 not sufficient for 32-nm half pitch [nm] NA 0.80 0.32 0.93 0.31 1.20 0.40 0.28 1.35 0.31 0.22
Slide 16: Single Exposure (like EUV) Litho requirements
Single Exposure (like EUV) Litho requirements Real CD is smaller than target CD Error caused by litho step CD error during litho process steps will result in smaller lines Extra CD errors are created during etch step Combined with litho CD error to a Final CD error Target CDlitho CD determined by 2
Slide 17: Litho Double Patterning Litho requirements
Litho Double Patterning Litho requirements Real CDlitho is smaller than target CDlitho Error caused by litho Target CDlitho CD determined by 8 error components; 2 x litho, 2 x etch and overlay: D CDlitho < 3,5% of CD Overlay < 7% of CD Final CD < 10% CD 1 st Photo CD errors during litho will result
Slide 18: Double line patterning; 32-nm half pitch Flash
Double line patterning; 32-nm half pitch Flash MASK A MASK B Pitch = 64nm Target Min Pitch 64nm k1 = 0.20 SPLIT + OPC Poly patterning Annular 0.8/0.5, X-Y polarized XT:1700i, 193nm - 1.2NA Co work ASML, Imec, Synopsys and Mentor Graphics Hard mask Poly
Slide 19: New software & algorithms required for Double Patterning
New software & algorithms required to split & optimize OPC and stitching for Double Patterning Memory Logic Original layout Pattern split NAND Flash DRAM Restricted Logic Random Logic Increasing Difficulty Challenges Correct decomposition OPC for decomposition Model-based stitching error compensatio
Slide 20: Spacer Double Patterning Litho requirements
Spacer Double Patterning Litho requirements Real CD is smaller than target CD Error caused by litho and etch trim patterning steps Sacrificial line patterning: A CD error during litho and etch process steps will result in smaller lines Line CD error propagates during spacer uniform deposition and et
Slide 21: CD and overlay litho budget challenge
CD and overlay litho budget challenge 3-4 # process steps relative to single exposure 2-3 # mask steps 20% 3% Spacer double patterning 3,5% 7% CD 7% 20% Overlay Litho double patterning Single exposure Litho exposure Equipment parameter as percentage of CD
Slide 22: Lithography Limits for ArF Single & Double Patterning
NA SE DPT SE DPT SE DE DPT 0.93 1.20 1.35 ArF Lithography Limits for ArF Single & Double Patterning NAND Flash Physical limit Double Patterning limit Double Exposure limit Single Exposure limit DRAM Logic NAND DRAM Logic
Slide 23: NA 1.55 requires new liquid, new glass and very low k1
NA 1.55 requires new liquid, new glass and very low k1 to extend to 32nm 100 65 45 32 22 16 11 year 2005 2007 2009 2011 2013 2015 half pitch 32 nm half pitch with 193 immersion extremely challenging [nm] NA 0.80 0.32 0.93 0.31 1.20 0.40 0.28 1.35 0.31 0.22 0.15 1.55 0.26 0.18 13.5 0.25 0.59 0.41 0.3
Slide 24: 29-nm imaging on interference set-up
29-nm imaging on interference set-up Version I Interferometer 85 nm ARC-29A, 50 nm PARIM850 resist Imaging results with Dupont IF169 beam splitter Fold mirror laser Wafer
Slide 25: Apertures, field sizes and refractive indices
Water based litho New fluid n>1.8 New lens material n>1.9 New resist N>1.8 Apertures, field sizes and refractive indices Second gen fluid n=1.65 Quartz lens material n = 1.57 Second gen fluid n=1.65 New lens material n>1.9 7% 15% 4% 15%
Slide 26: Historic reduction stepper imaging technology changes
Historic reduction stepper imaging technology changes 3.3 Diffraction limit [nm] >2010 > 6 193 nm/HI 1031 >2010 >10 13 nm/ vacuum 2006 193 nm/water - Failed 157 nm/air 2002 193 nm/air 1995 248 nm/air 1989 365 nm/air - 1980 - 436 nm/air Incremental Improvement % Production Insertion Incubation time [
Slide 27: EUV the only high volume opportunity
100 65 45 32 22 16 11 year 2005 2007 2009 2011 2013 2015 half pitch EUV required for 32 nm as cost reduction for double patterning and more extendable technology than non water immersion EUV the only high volume opportunity [nm] NA 0.80 0.32 0.93 0.31 1.20 1.35 0.15 1.55 0.26 0.18 13.5 0.25 0.59 0.4
Slide 28: Installation of EUV
Installation of EUV in progress (Dec. 2006) Albany Leuven
Slide 29: Full field, through focus lines, contacts
Full field, through focus 40 nm lines, 55 contacts Resist: MET-2D, ~18 mJ/cm 2 NA=0.25 = 0.5 (conventional illumination) Field point -10.6 mm -6.36 mm 6.36 mm 10.6 mm Focus
Slide 30: EUV source power progress
0.1 1000 2001 2003 2005 2007 2009 2011 Year Planned performance Source power progress has been increasing supplier 2 supplier 1 supplier 3 supplier 4 180 W 100 W/hr @ 10 mJ/cm 2 Actual data Sn Xe Sn Xe
Slide 31: Likely technology roadmap
Low k 1 challenge half pitch 2015 2013 2011 2009 2007 2005 year 11 16 22 32 45 65 100 Pitch relaxation or Double patterning Fluid/ material challenge Infrastructure challenge 0.37 0.53 0.45 0.41 0.57 0.35 0.41 0.59 0.25 13.5 0.18 0.26 1.55 0.15 0.22 0.31 1.35 0.28 0.40 1.20 0.31 0.93 0.32 0.80 NA [n
Slide 32: ASML 300mm Product Roadmap
ASML 300mm Product Roadmap High Index decision point 193nm
Slide 33: Content
Content The demand for shrink continues Litho roadmap Litho integration Litho cost Summary
Slide 34: High k1: Low Design to Wafer Integration
High k 1 : Low Design to Wafer Integration Design & Layout Mask Shop High k 1 (>0.5) : Independent Design, Mask Manufacture & Wafer Processing Wafer Fab
Slide 35: Litho aware design constrains
Litho aware design constrains Low k 1 : High Design to Wafer Integration Low k1 (<0.4) : Integration of design, mask and Lithography processes Design for Manufacturing DFM Application Specific Manufacturing Design space Manufacturing space
Slide 36: ASML & Brion: Integrated manufacturing solution
ASML & Brion: Integrated manufacturing solution Brion Ultra fast verification & RET/OPC LithoCruiser: Source & Mask Optimization Scanner data & optimization ASML MaskTools Reticle Enhancement Technologies Chrome-less Phase-shift technology (CPL) Scattering Bars placement technology Production Litho
Slide 37: Extending Lithography is driving Integration of Design, Mask, Process and Exposure
IC Design RET mask 193 i Process flow Extending Lithography is driving Integration of Design, Mask, Process and Exposure 193 Immersion with hyper NA and low k1 capability IC design for manufacturability, DFM Source-mask optimization, Litho, RET&OPC Process flow optimized for low contrast imaging, op
Slide 38: Content
Content The demand for shrink continues Litho roadmap Litho integration Litho cost Summary
Slide 39: Increased litho process complexity drives cost
KrF ArF ArF ArFi ArFi DPT 130nm 90nm 65nm 45nm 32nm 32nm EUV 32nm Spacer DPT Increased litho process complexity drives cost Hard Mask Etch Resist Organic BARC Hard Mask Expose Develop Inorganic BARC Metrology Strip & Clean Top Coat DPT = Double Patterning
Slide 40: Cycle time of multiple exposure strategies increases
A Process (Single Exposure) Lithography Lithography B Process (Double Exposure) Cycle time Cycle time Higashiki, Tosiba, Santa Clara, SPIE march 06 Cycle time of multiple exposure strategies increases
Slide 41: Lithography System Price Evolution
Wafer Size Wavelength Platform Aperture Lithography System Price Evolution 1M 10M 100M 1985 1990 1995 2000 2005 2010 Year i-line 300mm 200mm 150mm KrF ArF ArFi EUV Stepper Step & Scan Dual Stage 0.4 0.5 0.6 0.7 0.8 0.93 1.2 €4 0M?
Slide 42: ASML System Throughput Improvement
200mm Stepper Future DPT requirement 150mm Stepper 200mm Scanner TWINSCAN 300mm Scanner ASML System Throughput Improvement 1985 1990 1995 2000 2005 2010 XT:1450G g-line i-line KrF ArF Immersion Wavelength Year of Introduction XT:1400Ei XT:1700Fi XT:1900Gi
Slide 43: Litho cost per layer: estimates for 32nm
Defect free mask / no pellicle Source power / resist sensitivity Pattern split Process complexity Overlay & CDU Pattern split Process complexity CDU control Challenges Litho cost per layer: estimates for 32nm * Mask cost based on 5000 wafers / mask usage 193nm Spacer DPT 193nm Litho DPT EUV Fixed Op
Slide 44: Lithography cost affordability
XT:1400 65 nm 0.93 NA ArF 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2000 2002 2004 2006 2008 2010 2012 Lithography cost affordability: Cost per minimum Feature 2 continuous shrink 32 nm 0.25 NA EUV (60 WPH) 22 nm 0.25 NA EUV (100 WPH) XT:1700i 45 nm 1.2 NA ArFi AT:850 130 nm 0.8 NA KrF XT:1250 90
Slide 45: Content
Content The demand for shrink continues Litho roadmap Litho integration Litho cost Summary
Slide 46: Shrink rates versus tool introduction
R&D R&D Shrink rates for Logic, DRAM, and NAND flash versus tool introduction at k 1 0.27 and 0.40 Source: Various customers, dates determine production start/qualification Year ASML Product Introduction XT:1400 XT:1700i AT:1200 AT:850 XT:1900i k1=0.4 k1=0.27 Logic DRAM NAND To enable continued shri
Slide 47: Summary lithography roadmap
Summary lithography roadmap Water based immersion will capture the 40 nm half pitch using 1.35 NA 193 nm lithography. Non water based immersion needs new lens materials to increase resolution capability significantly: New fluid technology advantage for full field resolution limited by existing lens
Slide 48: Summary lithography integration and cost
Summary lithography integration and cost Extension of 193 nm is requiring tighter CD and overlay, yielding DPT split and processing. This will drive the integration of design, mask, process and exposure, resulting in integrated DFM solutions as well as mask and application specific manufacturing. EU
Slide 49: Commitment
Commitment
Asml Holding — ISS (Industry Strategy Symposium), Half Moon Bay 2007 on 6ix