Monolithic Power Systems, Inc. · NASDAQ:MPWR

Monolithic Power Systems — Technical Presentation (November 2022)

18 slides from Monolithic Power Systems's technical presentation, November 2022

  1. Slide 1: Designing a Power Tree for an Automotive SoC

    Designing a Power Tree for an Automotive SoC Pre-Regulator Design Webinar will begin at 10:00 AM CET | 1:00 AM PST | 4:00 AM EST November 2022

  2. Slide 2: Agenda

    Agenda Introduction Understanding the System-On-Chip (SoC) Power Requirements Challenges for Automotive Batteries Selecting the Right Pre-Regulator Architecture Setting the Pre-Regulator Bus Voltage How to Select the Optimal IC System Protections Conclusion

  3. Slide 3: Introduction

    Introduction ADAS and infotainment system-on-chips (SoCs) are offering increasingly higher computing power to enable high-level autonomous driving and optimized user experience. Increased Power Consumption Demanding Converter Performance Higher Power Density Autonomous drive platform 1

  4. Slide 4: Understanding the SoC Power Requirements

    Understanding the SoC Power Requirements A generic SoC’s power requirements is shown below, including the required voltage for each rail, expected current peaks, load change magnitude, and the required accuracy. Current Transient Slew Rate Voltage Rail Name Voltage (V) Notes (A) Load (A) (A/µs) Tole

  5. Slide 5: Understanding the SoC Power Requirements

    Understanding the SoC Power Requirements Voltage (V) 0.875 (+3%) Rail Voltage 0.85 Voltage tolerance 0.825 (-3%) Current (A) Time (us) Max Current 60 40 ΔI Transient Load 20 Slew rate Δt 0 0 10 20 30 40 50 60 Time (us) 3

  6. Slide 6: Challenges in Automotive Batteries

    Challenges in Automotive Batteries 4

  7. Slide 7: Selecting the Right Architecture

    Selecting the Right Architecture DC/DC0 0.85V 60A VIN EN SW0 DC/DC1 1.8V 5A Generic SoC VIN VDD_CORE EN SW1 1V8_GPIO DC/DC2 3.3V 5A 3V3_GPIO VIN Up to 40V, EN SW2 1V8_analog Reverse polarity, PCIe Warm Crank DC/DC3 1.8V 1.5A VIN MIPI Regulated Bus EN SW3 Battery ???? DDR_VDD DC/DC4 0.85V 1.5A DDR_VD

  8. Slide 8: Selecting the Right Architecture

    Selecting the Right Architecture The first step is to decide on a topology based on the system specifications: System Specifications Topology Must operate during a warm-crank event Buck converter Must operate during a warm-crank event, and Buck converter and some circuits require a voltage exceeding

  9. Slide 9: Setting the Pre-Regulator Voltage

    Setting the Pre-Regulator Voltage • The Intelli-phase converter for the high current rail (DC/DC0) requires VIN ≥ 5V • The other DC/DC (1 - 7) only require VIN ≥ 3.3V because all rail voltages are ≤3.3V 7

  10. Slide 10: Setting the Pre-Regulator Voltage

    Setting the Pre-Regulator Voltage To check if it makes sense to use a dedicated 3.3V bus for the lower current rails, calculate the power for regulator 2, and the output current in each case: σ7 Vn xIn 1.8x5+3.3x5+1.8x1.5+0.85x1.5+0.75x1.5+1.05x6+0.6x6 PPRE−REG2 = 1 = = 45.5W η 0.89 P 45.5 IPRE−REG2

  11. Slide 11: Setting the Pre-Regulator Voltage

    Setting the Pre-Regulator Voltage Should the 5V bus be consolidated into a single converter? VxI 0.85x60 PPRE−REG1 = = = 57.3W PPRE−REG2 = 45.5W η 0.89 PRE-REG1 PPRE-REG= 102.8W VIN EN SW 5V/20.6A 5V Bus IPRE-REG = 20.58A Battery If separated: PRE-REG1 VIN 5V/11.5A To Core DC/DC EN SW IPRE-REG1= 11.

  12. Slide 12: How to Select the Optimal IC

    How to Select the Optimal IC COMPILED REQUIREMENTS • Tolerate load dump up to 40V • Operate in warm-crank down to 6V • Output current capability above 11.5A When applying filters to the product catalog, no single part is capable of 11.5A. However, two MPQ4360 devices can be paralleled to achieve a 1

  13. Slide 13: MPQ4360-AEC1 Overview

    MPQ4360-AEC1 Overview Master VIN VIN BST EN VOUT FREQ FEATURES SW SYNCIN MPQ4360 SYNCO • Wide 3.3V to 45V Input Voltage (VIN) Range FB VCC ICS SS • 6A Output Current (IOUT) with Multi-Phase Capability GND • Low IQ (10μA Sleep Mode, 1μA Shutdown Mode) ICS Slave • Configurable Switching Frequency (fSW

  14. Slide 14: System Protection

    System Protection The MPQ4360 Pre-regulator can protect the systems against load dump voltage, but can be damaged when the battery polarity is reversed. • The typical protection is placing a diode in series with the input line. • In this SoC system, the input current can exceed 8A, which causes a ve

  15. Slide 15: MPQ5850-AEC1 Overview

    MPQ5850-AEC1 Overview The MPQ5850-AEC1 is an ideal diode controller VIN M1 VOUT that uses an N-channel MOSFET emulating a diode. GATE SOURCE DRAIN RES SW MPQ5850 • During forward conduction the FET is fully Power Enable EN/UVLO PG Good OFF ON GND turned on to minimize the power loss. VOUT • In the e

  16. Slide 16: Conclusions

    Conclusions MPQ4360 5V/11.5A MPQ5850 VIN To Core DC/DC EN SW MPQ4360 VIN Battery EN SW MPQ4360 5V/9A To Low Current VIN DC/DC EN SW MPQ4360 VIN EN SW 14

  17. Slide 17: Conclusions

    Conclusions There are 3 main topics to consider when designing the pre-regulator for an SoC: • Select an IC that can operate correctly under all automotive battery conditions • A 5V bus voltage is typically more cost-effective, but can be inadequate for certain applications • When the input current

  18. Slide 18: Q&A

    Q&A Let us know your questions.

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