Synopsys, Inc. · NASDAQ:SNPS
Synopsys — Technical Presentation (2004)
18 slides from Synopsys's technical presentation, May 5, 2004
Slide 1: An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters Institute for Computer Aided Circuit Design Friedrich-Alexander-University of Erlangen-Nuremberg Reinhard Hofmann Institute for Computer Aided Circu
Slide 2: Content
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters Content motivation overview about design environment behavioral levels for simulation high speed simulation models from behavioral to circuit level conclusions and future work Institute for Computer Aided Circuit Design Rein
Slide 3: Motivation
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters Motivation " ! assumption: quantizing error largely uncorrelated from sample to sample error has statistical properties that are independent of the signal N: number of quantizer bits L: order of modulator OSR: oversampling r
Slide 4: Behavioral Simulation
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters Behavioral Simulation Why - behavioral simulation? – checking out different possibilities (e.g. order of modulator, word length of quantizer, oversampling ratio, ...) – find out minimum system costs – system may be instable
Slide 5: Requirements
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters Requirements need to develope application dependent behavioral models necessary to verify the models wastes expensive time during developement Solution: developement of widely configurable models Institute for Computer Aided
Slide 6: Overview
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters Overview configurable behavioral models (written in C) code optimized for high simulation speed GUI to configure models special analysis tools (SNR, pattern noise, etc.) model generator for modulator (schematic) integrated i
Slide 7: Overview of Modelling Levels
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters Overview of - Modelling Levels level 0 C−model mathematical description level 1 C−model system theoretical description level 2 H(z) H(z) ADC decimator DAC behavioral description Institute for Computer Aided Circuit Design Re
Slide 8: Level 0
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters Level 0 mathematical description of an ideal system model parameters – anti-alias filter (order, 3 dB frequency) – order of modulator – oversampling ratio – word length of quantizer – downsampling ratio – order of decimation
Slide 9: Example of Simulation Level 0 (Power Density at Modulator Output)
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters Example of Simulation Level 0 (Power Density at Modulator Output) Institute for Computer Aided Circuit Design Reinhard Hofmann 9
Slide 10: Level 1
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters Level 1 system theoretical description of a real system model parameters – all level 0 parameters – gain of integrators – leakage of integrators – gain error of DA converter – offset of quantizer simulation results – time an
Slide 11: Example of Simulation Level 1 (Pattern Noise)
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters Example of Simulation Level 1 (Pattern Noise) Institute for Computer Aided Circuit Design Reinhard Hofmann 11
Slide 12: Level 2
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters Level 2 generated behavioral descriptions of modules schematic generated automatically usable as component Institute for Computer Aided Circuit Design Reinhard Hofmann 12
Slide 13: Sample of Generated Behavioral Code
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters Sample of Generated Behavioral Code when (event_on(clk)) { if (clk == l4_1) { vin_dac = v(in_dac_p) − v(in_dac_n) vin_val = v(inp)−v(inn) vout_temp = vout_state+faktor*(vin_val − dac_faktor*vin_dac) schedule_event(time, vout
Slide 14: Generated Schematic of an SC-Integrator
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters Generated Schematic of an SC-Integrator Institute for Computer Aided Circuit Design Reinhard Hofmann 14
Slide 15: Analysis of a Quantizer
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters Analysis of a Quantizer monte carlo analysis transition density plot determine specification Institute for Computer Aided Circuit Design Reinhard Hofmann 15
Slide 16: Using Design Environment
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters Using - Design Environment simulation parameter simulation parameter adjustment results automated parameter passing structural model automated continue with design structural generation Institute for Computer Aided Circuit D
Slide 17: Summary and Conclusions
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters Summary and Conclusions highly optimized behavioral models mathematical and system theoretical description get specifications by simulation hierarchical design flow checking out different possibilities (e.g. order of modulat
Slide 18: Future Work
An Interactive Design Environment for Delta-Sigma Analog-Digital-Converters Future Work development of further models and model generators to provide design support downto transistor level provide different techniques for modulator (e.g. switched current) implement support for cascaded feedback stru