Applied Materials, Inc. · NASDAQ:AMAT
Applied Materials — Investor Day (September 2021)
57 slides from Applied Materials's investor day presentation, Sep 8, 2021
Slide 1: ICAPS and Packaging Master Class
ICAPS AND PACKAGING MASTER CLASS September 8, 2021
Slide 2: Forward-Looking Statements and Other Information
Forward-Looking Statements and Other Information Today’s presentations contain forward-looking statements, including those regarding anticipated growth and trends in our businesses and markets, industry outlooks and demand drivers, technology transitions, our business and financial performance and m
Slide 3: Welcome
2021 Master Classes WELCOME Michael Sullivan Corporate Vice President Head of Investor Relations ICAPS and PACKAGING MASTER CLASS | September 8, 2021 Applied Materials External Use
Slide 4: Upcoming Investor Events
UPCOMING INVESTOR EVENTS MASTER CLASSES September October 8 18* ICAPS Process & Control Advanced & Packaging AppliedPRO™ * Projected Date Applied Materials External Use
Slide 5: Agenda
AGENDA 9:00 PART 1 HOST: Mike Sullivan Foundry-Logic Growth Thesis Fireside Chat | Tom Caulfield, Ph.D., GlobalFoundries 9:15 PART 2 HOST: Sundar Ramamurthy, Ph.D. ICAPS and Advanced Packaging Introduction ICAPS | Michael Chudzik, Ph.D. Packaging | Nirmalya Maity, Ph.D. 9:55 PART 3 HOST: Sundar Rama
Slide 6: Takeaway
TAKEAWAY Messages 1. ICAPS markets fuel data generation at the edge and demand for leading-edge logic and memory in the cloud 2. Advanced packaging enables the PPACt™ benefits associated with Moore’s Law to continue 3. Applied's unique portfolio breadth enables outperformance in ICAPS and advanced p
Slide 7: AI Era Will Be Biggest Age of Computing
Semiconductor Industry Revenue ($B) 1,200 2030 Semi forecast = $1T 1,000 2018 800 Machine generated data surpasses human generated data Semi revenue = $466B ERA 4 : AI 600 2002 First Blackberry smartphone introduced 400 1990 Semi revenue = $141B Global PC sales surpass 25M units ERA 3 : Mobility Sem
Slide 8: Semi Growth No Longer Limited by Human Consumption
Data Generation By Category (ZB) 157 2018 AUTOMOTIVE MACHINE > HUMAN HOME IOT CROSSOVER DATA-CENTRIC WORLD 92 APP-CENTRIC WORLD INDUSTRIAL IOT 55 30 13.8 6.6 0.1 0.3 0.8 1.6 3.1 HUMAN 2015 2016 2017 2018 2019 2020 2021E 2022F 2023F 2024F 2025F SEMI GROWTH NO LONGER LIMITED BY HUMAN CONSUMPTION Sourc
Slide 9: Industry 1.0 to Industry 4.0
INDUSTRY 4.0 INDUSTRY 3.0 INDUSTRY 2.0 INDUSTRY 1.0 Cyber Physical Automation, Systems, internet of Mass production, computers Mechanization, things, networks assembly line, and electronics steam power, electrical energy weaving loom 1784 1870 1969 TODAY Applied Materials External Use
Slide 10: AI = Actionable Insight
TETHERED EDGE BATTERY EDGE EDGE COMMUNICATIONS CLOUD DATA CENTER DATA CENTER Faster, higher-bandwidth AI computing to make Explosion of communications to sense of all the data data generation move data around and create value AI = ACTIONABLE INSIGHT Applied Materials External Use
Slide 11: Silicon Content Growing as Everything Gets Smarter
Semi content per unit 2015 2020 2025F HIGH END SMARTPHONE $100 $170 $275 AUTO (GLOBAL AVERAGE) $310 $460 $690 DATACENTER SERVER (CPU + ACCELERATOR) $1,620 $2,810 $5,600 SMARTHOME (GLOBAL AVERAGE) $2 $4 $9 SILICON CONTENT GROWING AS EVERYTHING GETS SMARTER Source: Applied Materials Applied Materials
Slide 12: Semiconductor Industry Revenues
Semiconductor Industry Revenues $B 1,000 800 600 400 First $200B ~40Yrs 200 ~17Yrs ~7Yrs ~4Yrs 0 2022F 2024F 2026F 2028F 2030F 1960 1962 1964 1966 1968 1970 1972 1974 1976 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010 2012 2014 2016 2018 2020 ACCELERATING TREND
Slide 13: Historical WFE Mix
Historical WFE Mix Trailing Nodes Foundry / Logic vs. Memory Memory mix consistent over time <45% 10-year and 20-year averages: Foundry / Logic >55% Leading Nodes Foundry / Logic 10-year average: Leading nodes ~2/3 Trailing nodes ~1/3 10-Year Average Source: Gartner, VLSI, Applied Materials Appl
Slide 14: ICAPS and Packaging Technology
ICAPS and Packaging Technology Sundar Ramamurthy, Ph.D. Group Vice President GM Epi, ICAPS and Packaging ICAPS and PACKAGING MASTER CLASS | September 8, 2021 Applied Materials External Use
Slide 15: Applied = PPACt Enablement Company
Applied = PPACt Enablement Company™ Unit process Unique Actionable insight / leadership and combinations time to market broadest portfolio of technologies acceleration MASTER ICAPS & Advanced Packaging Process Control & AppliedPRO™ CLASSES Today Oct 18 Applied Materials External Use
Slide 16: Time-to-Market
ENABLED BY New architectures PERFORMANCE New structures / 3D Time-to-Market New materials New ways to shrink POWER AREA-COST Advanced packaging NEW INDUSTRY PLAYBOOK FOUNDATION IS MATERIALS ENGINEERING Applied Materials External Use
Slide 17: ICAPS & Advanced Packaging
ICAPS & ADVANCED PACKAGING ICAPS ADVANCED PACKAGING Michael Chudzik, Ph.D. Nirmalya Maity, Ph.D. Vice President of Technology Corporate Vice President Advanced Packaging Applied Materials External Use
Slide 18: ICAPS Nodes Leading Edge
TETHERED EDGE BATTERY EDGE EDGE COMMUNICATIONS CLOUD DATA CENTER DATA CENTER ICAPS NODES LEADING EDGE Applied Materials External Use
Slide 19: Unique Product Portfolio + Integrated Solutions
Unique Product Portfolio + Integrated Solutions CREATE Materials deposition Metal Dielectric Selective Epitaxy Plating ALD Deposition Deposition Deposition Only company with SHAPE Materials removal Process + metrology Etch Planarization Selective Removal Full flow chip lab Full flow packaging lab MO
Slide 20: ICAPS Markets
ICAPS IoT Comms Auto Power Sensor Applied Materials External Use
Slide 21: New Technologies Help Silicon Carbide Chipmakers Transition to 200mm
September 8, 2021: “New Applied Materials Technologies Help Leading Silicon Carbide Chipmakers Accelerate the Transition to 200mm Wafers and Increase Chip Performance and Power Efficiency” Applied Materials External Use
Slide 22: Accelerating Power Technology Roadmap
Accelerating Power Technology Roadmap Electrification of the transportation industry is a rising trend, and we are accelerating this inflection point by leading the global transition from silicon to silicon carbide with our Wolfspeed technology. Delivering the highest-performing silicon carbide powe
Slide 23: ICAPS Materials Engineering Challenges and Opportunities
ICAPS Materials Engineering Challenges and Opportunities Michael Chudzik, Ph.D. Vice President of Technology Semiconductor Products Group ICAPS and PACKAGING MASTER CLASS | September 8, 2021 Applied Materials External Use
Slide 24: Biggest Computing Wave Yet
BIGGEST Computing Wave Yet 1,200 “IoT is expected to add over $1.1 T to the Global Semiconductor Industry Revenue ($B) 1,000 Economy by 2025, rising to >$1.5T by 2030.” The Economist / Transforma Insights 800 ERA 4 : AI 600 400 ERA 3 : Mobility 200 ERA 2 : PC + Internet ERA 1 : Mainframe 0 1980 1985
Slide 25: A Global Competition to Win the IoT Inflection
A Global Competition to Win the IoT Inflection Global Competition New Multi-Billion-Unit Markets Enabled by Semi Innovations “Worldwide Spending on Edge Computing Will Reach $250 Billion in 2024” IDC | Sep 23, 2020 Wearable Tech Smart Home Mobile Computing Image Sensor Power Devices RF Devices “Our
Slide 26: Innovative ICAPS Technologies Transforming the Edge
Innovative ICAPS Technologies Transforming the Edge RF technology for vehicle-to- Advanced CIS, professional- everything communications quality camera and video Photonic devices for 3D imaging MEMS sensors for biometric monitoring Power technologies extend range Wireless, bluetooth and NFC Radar, Li
Slide 27: Image Sensor Physics and Implications for Performance
Image Sensor Physics and Implications for Performance CMOS image sensor Pixel noise reduction Signal sensitivity improvement Electrons generated in a silicon photodiode (pixel) 𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆…
Slide 28: Reducing Pixel Noise with Surface Engineering
Reducing Pixel Noise with Surface Engineering High-value problem Solution Defect sites at the pixel surface are Low-damage etch followed by silicon regrowth with embedded charge sites for defect passivation sources of pixel noise DTI surface engineering module Device value SNR 1 Lower damage silicon
Slide 29: Improved Signal Sensitivity with New Materials for DTI
Improved Signal Sensitivity with New Materials for DTI High-value problem Solution Signal sensitivity is degraded when incoming light DTI created with a highly reflective aluminum layer co-optimized with escapes the pixel or is absorbed by the blocking layer pre- and post- processes to maximize sign
Slide 30: Transition to EV with ADAS Increases ICAPS Content by 4x
Transition to EV with adoption of ADAS increases ICAPS semiconductor content by 4x Internal Combustion Engine1 Electric Vehicle2 $190 $640 $737 $145 $132 $387 $71 $170 Power Devices Sensor (CIS, Microcontroller Other (General Power Devices Sensor (CIS, Microcontroller Other (General Photonics, etc.)
Slide 31: Power Device Physics and Implications for Performance
Power Device Physics and Implications for Performance Power MOSFET Improving power MOSFET performance A high-voltage, high-current semiconductor switch Increase mobility 𝜇𝜇𝑛𝑛 OFF State ON State Material selection (Si, SiC, GaN), crystal orientation Minimize crystal defects in the bulk or at the…
Slide 32: Reducing Surface Defects | Why This is Difficult
Reducing Surface Defects | Why This is Difficult High-Value Problem Solution Electron mobility is degraded by crystal Single-wafer CMP with higher down force and optimized consumables defects originating from the SiC substrate to minimize surface defects Average roughness Material removal rate Pre-C
Slide 33: Increasing SiC MOSFET Mobility and Lowering Resistance
Increasing SiC MOSFET Mobility and Lowering Resistance High-Value Problem Solution Bulk defects in SiC caused by implant Room-temperature implant damages crystal; hot implant allows crystal damage to damage reduce electron mobility heal, reducing RON I D : Drain current 𝑤𝑤𝐷𝐷 RON : On resistance…
Slide 34: Organized to Address ICAPS Opportunities
Organized to Address ICAPS Opportunities Unit process Unique Time-to-market leadership and combinations acceleration broadest portfolio of technologies Metal Epi Implant Deposition Co-optimization of Integrated materials processes / tools solutions Dedicated and partner ICAPS device labs/fabs Etch P
Slide 35: Advanced Packaging Challenges and Opportunities
Advanced Packaging Challenges and Opportunities Nirmalya Maity, Ph.D. Corporate Vice President Advanced Packaging ICAPS and PACKAGING MASTER CLASS | September 8, 2021 Applied Materials External Use
Slide 36: Time-to-Market
ENABLED BY New architectures New structures / 3D Time-to-Market New materials New ways to shrink Advanced packaging NEW INDUSTRY PLAYBOOK FOUNDATION IS MATERIALS ENGINEERING Applied Materials External Use
Slide 37: Biggest Computing Wave Yet: Connecting and Stacking Dies
BIGGEST Connecting & stacking dies Computing Wave Yet Maximize system-level performance 1,200 1,000 Semiconductor Industry Revenue ($B) Package stacking Form factor (area/thickness) Power (battery life) 800 Hybrid-bonding ERA 4 : AI Package mounting on PCB 600 Protecting and connecting dies from out
Slide 38: Gordon Moore 1965 Prediction on Disaggregation
In 1965, Gordon Moore predicted both the exponential increase of transistors on a chip, and conditions that would drive the disaggregation of the system-on-chip It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected https:
Slide 39: Packaging Enables PPACt Scaling
Packaging Enables PPACt™ Scaling Shorter, parallel interconnects Higher I/O 30x lower power Reduced latency PCB chip-to-chip connection Power Lower power vs. hybrid bonding Performance GDDR5 HBM Area 3D stacking GPU ~3X system Tighter integration GPU performance Many chips per package >50% lower pow
Slide 40: System Integration with Emerging 2D and 3D Interconnects
System Integration with Emerging 2D and 3D Interconnects THROUGH-SILICON VIA HYBRID BONDING 3D Interconnects (TSV) Through-Silicon Via (TSV) Chip 1 Hybrid bonding1 Source: TechInsights (Chipworks) IMX260 Camera Module Report, 2016 Chip 2 MICRO- Polymer RDL FLIP-CHIP BUMP BUMP 2D Interconnects
Slide 41: Packaging System Interconnect Scaling Roadmap
Packaging System Interconnect Scaling Roadmap Hybrid Bonding (chiplet stacking) Through-Silicon Via (chip stacking) I/O density (finer pitch) Better power efficiency w/ 10,000 ~ 1M I/O / mm finer pitch, shorter lengths 2 Power: <0.05 pJ / bit Microbumps (chip stacking) < 10,000 I/O / mm2 > 0.1 pJ /
Slide 42: Packaging to Enable Higher Density and Performance
Packaging to Enable Higher Density and Performance Connections initiate Redistribution layer routes TSV routes connections from DRAM die center connections to edge through silicon die Top View Single or two die wire-bonded 2-4 die on package 4+ die on package onto package Aluminum RDL and wire-bonde
Slide 43: Through-Silicon Via Fabrication and Backside Reveal
Through-Silicon Via Fabrication and Backside Reveal TSV Formation Centris ® Sym3® Via Etch Producer® InVia® CVD Endura® Ventura® PVD Nokota® Raider® ECD Reflection® LK CMP Incoming TSV Etch CVD Liner PVD Barrier TSV Cu Planarize Wafer Bottom Open (Via Last) and Seed Plating Remove Cu/Barrier Backsid
Slide 44: Solving TSV Extendibility Challenges
Solving TSV Extendibility Challenges Electrical Isolation at Low Complete TSV Fill with Copper Co-Optimizing Processes Temperatures Dielectric Constant Scalloped Capacitance Discontinuous Cu Fill Edges & Leakage Cu Seed Voids 10µm x 100µm SiN InVia <10-12 5 x 50 A/µm2 Leakage Current 3 x 50 <5x10-16
Slide 45: Hybrid Bonding: Enabling 10K-1M/mm2 I/O Density
Hybrid Bonding: Enabling 10K-1M/mm2 I/O Density Paradigm What is hybrid bonding? The potential of hybrid bonding Shortest connections with face-to-face chip bonding Ultimate bonding solution – outstanding performance Applied Materials modeling data 0 Die-to-Wafer Hybrid Diced wafer -2 Bonding Wafer-
Slide 46: Optimization of Complete Process for Highest Bonding Yield
Optimization of Complete Process for Highest Bonding Yield Pad Formation: current Applied Materials product portfolio + Bonding: in partnership Producer® CVD Producer® Etch Endura® Mustang® Reflexion® LK Substrate Dielectric stack Damascene RDL / Barrier / Seed PVD Copper pad fill CMP w ith tuned Su
Slide 47: Processing Large Packages and Substrates
Processing Large Packages and Substrates System integration of multiple chips on package Advanced large substrate PVD technology Panel-level packaging Package size grows Applied Topaz™ PVD Acquisition of Tango Systems Panel PVD technology ADVANCED SUBSTRATE Semi quality processing Panels up to 600x6
Slide 48: Organized to Address Packaging Challenges
Organized to Address Packaging Challenges Unit process Focus on enabling Co-optimized leadership and valuable inflections technologies broadest portfolio Metal Dielectric Plating Deposition Deposition Heterogeneous Integration Dedicated advanced packaging lab Etch Planarization Inspection Advanced S
Slide 49: ICAPS and Packaging Growth Opportunities
ICAPS and Packaging Growth Opportunities Sundar Ramamurthy, Ph.D. Group Vice President GM Epi, ICAPS and Packaging ICAPS and PACKAGING MASTER CLASS | September 8, 2021 Applied Materials External Use
Slide 50: Going Beyond Unit Process Tools to Deliver Solutions
Going Beyond Unit Process Tools to Deliver Solutions FASTER TIME TO MARKET, HIGHER VALUE, STICKIER UNIT PROCESS LEADERSHIP + BROADEST PORTFOLIO CO-OPTIMIZATION OF ~40% of our products PROCESSES / TOOLS now co-optimized INTEGRATED ~30% of our products MATERIALS now integrated SOLUTIONS ACTIONABLE INS
Slide 51: Improved Signal Sensitivity with New Materials for DTI
Improved Signal Sensitivity with New Materials for DTI High-value problem Solution Signal sensitivity is degraded when incoming light DTI created with a highly reflective aluminum layer co-optimized with escapes the pixel or is absorbed by the blocking layer pre- and post- processes to maximize sign
Slide 52: New Materials Co-Optimized to Improve CIS Capabilities
New Materials Co-Optimized to Improve CIS Capabilities Image sensors with AI functionality are going to change how we engage with the world around us. At the heart of this is Sony’s CMOS sensor, where innovations in process technologies are required to improve performance attributes such as sensitiv
Slide 53: WFE Mix
WFE Mix ICAPS Nodes ICAPS Nodes Memory Memory <45% <45% Leading Nodes Leading Nodes = memory, = foundry-logic 10-Year Average 2018-2021e Source: Gartner, VLSI, Applied Materials Applied Materials External Use
Slide 54: Positioned for Growth in Packaging
Positioned for Growth in Packaging Early innings of multi-year growth Packaging revenue >$800M in FY’21 #1 in bond pad, bump and TSV Broad product portfolio + full-flow lab ~$500M Key eco-system partnerships Delivering system level PPACt gains R, power, area, performance Year FY’20 FY’24F TS
Slide 55: Biggest Computing Wave Yet: Connecting and Stacking Dies
BIGGEST Connecting & stacking dies Computing Wave Yet Maximize system-level performance 1,200 Semiconductor Industry Revenue ($B) 1,000 Package stacking Form factor (area/thickness) Power (battery life) Hybrid-bonding 800 ERA 4 : AI Package mounting on PCB 600 Protecting and connecting dies from out
Slide 56: Takeaway
TAKEAWAY Messages 1. ICAPS markets fuel data generation at the edge and demand for leading-edge logic and memory in the cloud 2. Advanced packaging enables the PPACt™ benefits associated with Moore’s Law to continue 3. Applied's unique portfolio breadth enables outperformance in ICAPS and advanced p
Slide 57: Applied Materials External Use
Applied Materials External Use