Etron Technology, Inc. · TPEX:5351
Etron Technology — ESWEEK 2025
66 slides from Etron Technology's conference presentation, Sep 29, 2025
Slide 1: Challenges in the Symbiosis between Semiconductors and AI
ESWEEK 2025, September 29, 2025 Challenges in the Symbiosis between Semiconductors and AI: Optimizing Cost-Performance-Power through Second-Path Moore’s Law Scaling, Especially for Edge-AI Embedded Systems Nicky Lu PhD, Stanford; National Academy of Engineering (NAE) & Inventors (NAI), USA Chair (20
Slide 2: Diffusion-in-Transformer: Converting Token Intelligence to Action
Diffusion-in-Transformer: Converting TOKEN (word, text, picture) Intelligence ACTION Sources: Introducing Sora Video by OpenAI; Sound Effects by ElevenLabs, March ‘24 2
Slide 3: Diffusion-in-Transformer: Converting Token Intelligence to Action
Diffusion-in-Transformer: Converting TOKEN (word, text, picture) Intelligence ACTION Sources: Introducing Sora Video by OpenAI; Sound Effects by ElevenLabs, March ‘24 3
Slide 4: Today's Talk
Album-cover design by AI Theme Song for Today’s Talk Lyrics provided by us September 2025 by Using Suno 4
Slide 5: Milestone Events of Semiconductor/IC and AI
Nobel Milestone Events of Semiconductor/IC And AI Prize in Physics G. E. Hinton and John Hopfield ChatGPT (openAI) AI 1st Winter AI 2nd Winter Transformer Logic Theorist algorithm (1st AI program) 1970~1980 1990~2000 (Google) Allen Newell & AlphaGo Herbert A. Simon defeated John Clifford Shaw (RAND
Slide 6: Sources: John Chen, VLSI Symposium
Sources: John Chen, VLSI Symposium of Technology and Circuit, June 2025 6
Slide 7: VLSI → MCM → Board → Rack → Data Center
VLSI, Integrate at the Lowest Level Possible VLSI → MCM → Board → Rack → Data Center Si4.0 Booming ! Sources: John Chen, VLSI Symposium of Technology and Circuit, June 2025 7
Slide 8: Will Moore's Law and Dennard's Scaling Die?
But, Will the Driving Engine of Silicon Growth, Moore’s Law & Denard’s Scaling, Die As We Can Judge by Now in 2025? Challenge in 2015 if the Moore’s Law & the Denard’s Scaling Die ? 8
Slide 9: Semiconductor Industry Revenues & Lu's Perspective
Semiconductor Industry Revenues & Lu’s Perspective Heterogeneous US$B Integration AI × HI × IC + Intelligence N Civilization C&C Σ (HI New applications Heterogeneous A year ) Contents & Clouds Integration of Silicon+Non- years Number of HI Sub-systems Silicon (4.0) Integrated (HI＝ICH) System Softwar
Slide 10: Moore's Law: Transistors per Chip Doubling
Moore’s Law The Number of Transistors per Monolithic Chip Doubles Each 24 Months It’s an economic law driven by technology/transistor advancement, delivering optimized PPACT for Microelectronics (Better Power, Performance, Area, Cost, Time to Production) 106 V-NAND 1.33Tb (QLC) V-NAND 512 Gb (TLC) M
Slide 11: Why NAND Follows Moore's Law Scaling Better
Why NAND Follows Moore’s Law Scaling Better Than DRAM and Logic on #Transistors/Planar-Area Based on Device-Structure Inventions 3D Cell Array Structure Stacking 400 Layers One Straight Etching to Create Wordline through 400 Layers From 1bit/cell to 4bits/cell Heterogeneous Integration of Ce
Slide 12: New Semiconductor Growth by AI
New Semiconductor Growth by AI Before AI: One Killer Application One Time; AI Brings In N Killer Applications Simultaneously Semiconductor Si Industry Artificial Intelligence Mainframe Computer Personal Computer Notebook Internet IoT Automotive >10 Killer Applications Lu, 2015 12
Slide 13: Strong Market Driver from AI
Strong Market Driver from AI Semiconductor market ($B) 1296.9 1400 1146 1013.2 1200 896.6 377.9 1000 797.6 712.4 411 635.9 800 433.2 Billion 441.6 600 465.6 475.4 919 400 470.9 735 580 200 455 332 237 165 0 2024 2025 2026 2027 2028 2029 2030 AI technologies Non-AI Source: International Business Stra
Slide 14: AI Training Compute Outpacing Silicon Transistor Scaling
AI Training Compute Rate is Outpacing Silicon Transistor Scaling Rate GPT3 to GPT4 (68X/4yrs) Transistor Density (MTr/mm2) Training Compute (PFLOPs) 1E11 Transformer (750X/2yrs, 2018~2020) 3.14E82.15E10/2020~2024 GPT4 ~ Gemini ~1E9 CV/NLP/Speech (15X/2yrs) Claude 2 GPT3 Chinchilla Megatron LM Micro
Slide 15: Heat Dissipation Challenges in H.I.
Heat Dissipation Challenges in H.I.: XPU+Chiplets Burning Out 15
Slide 16: Global Energy Production Cannot Meet Computing Demands (I)
Global Energy Production Can NOT Meet Ever Rising Energy Demands for Computing (I) AI limited Scenario * ZIPS (1021 compute * instructions per second) * * aJ: attojoule (10-18 Joules) Source: SRC Jan 2021; After Nicky Lu, HIR 5th Annual Conference 2022 16
Slide 17: Review Current Symbiotic Growth of AI & SI
Review Current Symbiotic Growth of AI & SI on Future Challenges The symbiosis between AI and the semiconductor industry (SI) is highly positive, generating many new killer applications that expand the intelligenceN-driven industries and economies through advanced science and technology; However, it
Slide 18: Meindl's Analyses: Holistic and Hierarchical Methodology
Study of Ultimate Limits of Semiconductor and IC Meindl’s Analyses* : Holistic and Hierarchical Methodology 2. Material limit 3. Device limit 5. System limit 4. Circuit limit * 1. Fundamental Limit - Quantum limit - Thermodynamic limit * James Meindl, Stanford, RPI, Georgia Tech, study from 1978 to
Slide 19: Target Set by Dennard's Scaling
Device Scaling Methodology from Silicon1.0 (Line Scaling) (Si1.0) Line Scaling (2D MOSFET 0.7X scaling) Detailed Cross Sections for Scaled-Down Device Structure Robert Dennard and IBM, 1974 (0.7X) Doping concentration Ng (1.43X) Voltage V CV/I (0.7X) VI/A Power Density approaching 1 Target Set by De
Slide 20: From Line Scaling (Si1.0) to Area Scaling (Si2.0)
Device Scaling Methodology from Silicon1.0 (Line Scaling) to Si2.0 (Area Scaling), Accelerating Moore’s Economics at an Exponential Rate Drain (Si1.0) (Si2.0) Source Line Scaling Area Scaling (2D MOSFET 0.7X scaling) (3D FET+ >0.8X Line-Scaling) PPACT Can Not Meet Moore’s Law Demands Bulk Substrate
Slide 21: 1st Path Moore's Law Scaling: Area-Density Falling Behind
1st Path Moore’s Law Scaling (1PMLS)：Area-Density Falling Behind (PPACT) Peak Quoted Transistor Density For Standard Cell Optimization (MTr/mm2 :Million Transistor per Area) Technology Node Company A Company B Company C If obey Moore’s Law 22nm 18.8 Calculation Base on 16nm 16nm 28.9 (28.88) 14nm 44
Slide 22: 1PMLS: Power Density of Planar Transistors
1st Path Moore’s Law Scaling (1PMLS): Power Density of Planar Transistors Scaled to 22nm 1PMLS-A Phase (Planar Q : 1965 to 2011 ) Data Points Normalized Power Density 28nm C Planar (0.9V) 0.18um 0.13um 65nm 45nm 32nm 22nm Planar Planar Planar Planar FinFET Planar (1.0V) (0.7V) (1.8V) (1.5V) (1.2V) (
Slide 23: 1PMLS: Sharp Increase in Power Density
1st Path Moore’s Law Scaling (1PMLS)：Sharp Increase in Power Density (PPACT) beyond 22nm C 2025 Etron & TAT, Proprietary & All Rights Reserved 23
Slide 24: 1PMLS: Diminished Performance Scaling
1st Path Moore’s Law Scaling (1PMLS)：Diminished Performance Scaling (PPACT) beyond 16nm Technology Node C 2025 Etron & TAT, Proprietary & All Rights Reserved 24
Slide 25: Difficult to Scale eSRAM Cell Area
Difficult to Scale eSRAM Cell Area (Distinctive Area/F2 Metrics, F: Technology Node Given) 5500 Data Published 5250, 2nm eSRAM Cell Area (F2) 5000 ~ A - company ~~ ~ B - company 2211, 3nm C - company 2000 1500 C 1000 If followed by scaling 500 28 22 16 14 10 7 54 32 Technology Node Given (nm) 2025 E
Slide 26: The 2nd Path Moore's Law Scaling Down Part I
The 2nd Path Moore’s Law Scaling Down Part I: Optimized PPACT with Relaxed Litho by Device Design, eg. A CMOS Invention Can Deliver Better Scaling Results (Use 3D Sentaurus Modeling) Peak Quoted Transistor Density For Standard Cell Optimization (MTr/mm2 :Million Transistor per Area) Company If obey
Slide 27: NuFET: Vertical Fins by Vertical Insulator Fence
NuFET: Vertical Fins by Vertical Insulator Fence (VIF) & Raised STI (R-STI) Current Fin Body NuFET Body Hardmask Oxide fence Oxide fence (VIF) Nitride fence N+ R-STI C R-STI (VIF) Fin bottom z y z STI STI X y 27 & All Rights Reserved 27 2025 Etron & TAT, Proprietary
Slide 28: Dumbbell-Shaped Channel for Improved SCE
28 Dumbbell-Shaped Channel for Significantly Improved SCE (Short Channel Effect) WAA WCh NuFET Node Defined Nu8 Nu5.6 Nu4 Nu2.8 by Our C WAA (nm) 8 6 6 6 WCh (nm) 4* 4* 3* 3* WAA WCh *After Intel Channel Mobility Studies at 2024 IEDM Channel surface should be smooth under thermal oxidation process t
Slide 29: Damascene Technique for Internal Gate Spacers and Gate Formation
29 Damascene Technique for Internal Gate Spacers and Gate Formation NuFET NuGAA Node Defined Nu8 Nu5.6 Nu4 Nu2.8 Nu2 by Our Lgate (nm) C 12 11 10 9 8.5 R-STI Lgate-spacer 11 11 10 10 8 (nm) Litho Size for Gate 34 33 30 29 24.5 Formation (nm) z x y 2025 Etron & TAT, Proprietary & All Rights Reserved
Slide 30: Vertically Extended Gate to Reduce SCE and Leakage
30 Vertically Extended Gate (VEG) to Reduce SCE and Subthreshold Leakage 74 VEG Design Target (mV/dec) SSSS(mV/dec) 73 Gate Spacer Gate R-STI 72 Gate Spacer C Gate 71 70 -2 0 2 4 6 8 10 12 STI (nm) Gate over Fin Bottom Depth(nm) Gate over Fin Bottom Depth z (nm) Current Fin/Tri-gate FET NuFET x y 20
Slide 31: Accurate Leff Defined by PILI
31 Accurate Leff Defined by PILI (Partial Drain Isolation with L-structured Composite Insulators) Gate spacer C PILI 2025 Etron & TAT, Proprietary & All Rights Reserved 31
Slide 32: Semiconductor/Metal Junction with Landing Pad Design
32 Semiconductor/Metal Junction (SMJ) with Landing Pad Design/Formation： Achieved Ion Increase due to Tall Fin w/o Serious Reduction of S/D Resistances Traditional contact Our T-shape contact Contact Current Trench Crowding Spacer Gate Spacer Gate R-STI z EPI-S/D SMJ EPI-S/D C x 140 Total Current Nu
Slide 33: SMJ to Shrink Standard Cell for GAA Logic Gate
One Contribution of SMJ to Shrink STD Cell for GAA Logic Gate Innovative Frontside Power Sourcing between M0 and Source STD cell Top View Metal pitch (MP) Current VDD Cell height Vss Mx=M0 Gate R-STI SMJ SMJ Gate P+ Spacer R-STI C R-STI x VSS AA M0_PO VIA0 N- N- Gate M0_OD Well y Novel N+ N+ Inventi
Slide 34: Direct Metal Contacts to Both Gate & Landing Pad
Inventive Architecture for Direct Metal Contacts to Both Gate & Landing Pad (S/D) (Reduce 5-6 Critical Masks & 1 Simplified MEOL Processing Steps) Poly Gate: Lg M0_OD 5 M0_G 6 V_G 4 Critical Mask Tri- * V_SD 3 gate/FinFET NuFETs Description CT s 2 Lg S/D Epi S/D Epi Active Area AA AA 1 More relaxed
Slide 35: Key Device Parameters of 1PMLS vs NuFET Technologies
35 Key Device Parameters of 1PMLS vs NuFET Technologies in 2PMLS Company A- Company A FinFET GAAFET NuFETS NuGAA 8nm (Nu8) 5.6nm (Nu5.6) 4nm (Nu4) 2.8nm (Nu2.8) 2nm (Nu2) Key Parameter Single Vdd Single Vdd Dual Vdd Dual Vdd Dual Vdd 16 10 7 5 3 2 @ 0.75V @ 0.75V (Logic 0.7V/SRAM 0.75V) (Logic 0.65V
Slide 36: 2PMLS: Performance Enhanced
2nd Path Moore’s Law Scaling (2PMLS): Performance Enhanced (PPACT) +30% Per Generation Normalized Speed (a.u.) +20% Per Generation +10% Per Generation Data Points (1PMLS) NuFET Modeling Results (2PMLS) (Performance compromised by squeezing device area to a minimum size) C 16nm 28nm FinFET Planar 45n
Slide 37: eSRAM Cell Area Scaled Continuously in NuFET/NuGAA
37 eSRAM Cell Area Scaled Continuously in NuFET/NuGAA CPP Scaling (X-Axis) NN/NP/PP Pitch Scaling (Y-Axis) 2025 Etron & TAT, Proprietary & All Rights Reserved 37
Slide 38: 2PMLS: Reduction of Cell Area
2PMLS: Reduction of Cell Area in F2 Metrics and in Absolute Values 5500 Data Published 5000 eSRAM Cell Area (F2) A - company 6T SRAM Cell Areas: Absolute Value (um2) & Ratio ~~ B - company ~~ Technology 3000 Company A Node by NuFET C - company Node Authors 2500 8nm Nu8 0.0208 NuFET Modeling Results
Slide 39: Establish PPACT-Criteria from MDT as Microsystem Index
Establish PPACT-Criteria from MDT as Microsystem Index to Measure AI+SI Integration Efficiency for Most Productive ICR (Invention, Creation & Realization) Moore’s Law Dennard’s Scaling Methodology Transistors × 2 every 2 years Size ↓ Power/Area ≈ Same Enables continuous improvement in chip Maintains
Slide 40: Heterogeneous Integration Creates Silicon3.0
Heterogeneous Integration (HI) Creates Silicon3.0 New System Architecture by Dice in a Package: Multi-dimensional Layouts in Chips/Subsystems to Increase Integration in addition to Device Scaling mDIC (m-Dimensional Dice Integration Chip); m= 2, 2.5, 3, 4… Top View in Package For Example: RF or
Slide 41: Breakthrough in Si3.0: Known-Good-Dice Technology
A Breakthrough in Si3.0 : Known-Good-Dice (RAMs since 2000 ) Technology Enables Stacked-Dice System Chips Etron Proprietary & Copyright © 2007 All Rights Reserved, April 30 Etron Has Been Shipping KGD DRAM Since 2002. Shipments Have Totaled Over 3 Billion Units to-date. This Has Made Etron a Well-Re
Slide 42: A High-Volume Phone Maker Used HI inside iPhone 7
An Example: A High-Volume Phone Maker Used HI 3D Bare-Die+Chip+InFO inside iPhone 7 2016 42 Source: Chipworks.com; September, 2016 42
Slide 43: Si4.0 AI Era: Optimizing Monolithic & Heterogeneous Integration
A Must Si4.0 AI Era Coming Optimizing Monolithic & Heterogeneous Integration (MHI for Self-Smart μSystems by Function X Value Scaling Methodology (Si1.0) (Si2.0) (Si 4.0) AI Microsystem Era Function X Value Scaling Line Scaling Area Scaling Optimizing Monolithic & Heterogeneous (3D FinFET+ >0.7XLine
Slide 44: More MicroSystems Using Si4.0 Becoming Smarter
More MicroSystems Using Si4.0 Becoming Smarter Source: IEEE HIR Ch. 1, System Plus Consulting 44
Slide 45: More Networked Self-Smart MicroSystems Arising
More Networked Self-Smart MicroSystems Arising 45
Slide 46: Self-Smart MicroSystems Uplinked to Smart SuperSystems
More Self-Smart MicroSystems Uplinked to Smart SuperSystems within Individual Energy Contraint 46
Slide 47: SuperSmartSystems Enabled by Si4.0
Autonomous Smart Car City SuperSmartSystems with Many Self-Smart MicroSystems Enabled by Si4.0 Smart Super Factory Computer Source: Popular Mechanics, Forbe, Trend Micro 47
Slide 48: The Past: Independent Component Scaling
The Past: Traditional Moore’s Law: Independent Component Scaling Memory Storage/Cache • Latency ↓ • Capacity ↑ • Density ↑ SALING LIMITATION (Meindl’s Analysis) 1. Fundamental Limits: Quantum/Thermodynamic 2. Material Limits 3. Device Limits 4. Circuit Limits LOGIC 5. System Integration Limits: Von
Slide 49: 2nd Path Moore's Law Scaling Up Part II: Holistic OMHI
The 2nd Path Moore’s Law Scaling Up - Part II: Holistic OMHI (Optimized Monolithic & Heterogeneous Integration) System-Level Optimization Across Compute, Storage, Communication & Energy DATA PROCESSING AI/ML ∙ Computing Real Time Analysis Technology PPACT ENERGY MANAGEMENT MEMORY/STORAGE Power Effic
Slide 50: Integrated Scaling & Stretching Platform (ISSP)
The 2nd Path Moore’s Law Scaling Up : Integrated Scaling & Stretching Platform (ISSP) 50
Slide 51: PPACT-Criteria from OMHI as System Index
Establish PPACT-Criteria from OMHI as System Index to Measure AI+SI Integration Efficiency for Most Productive ICR (Invention, Cooperation & Realization) OMHI System Integration Traditional Scaling Metrology Holistic Optimization x System Maintains Device Feasibility while Enable Unified AI+SI Perfo
Slide 52: Taiwan Semiconductor Industry Milestones (1964-2025)
Taiwan Semiconductor Industry Milestones (1964-2025) Revenues of Taiwan Semiconductor (0.1 Billion USD) A Documentary Movie on Taiwan’s Chip Odyssey, 2025 Taiwan Semiconductor 2500 Revenues Ranked No. 2 in the World 2000-2004 Etron Pioneers Known Good Die (KGD) & Coins Heterogeneous Integration of S
Slide 53: Etron Group
Group IC Products Privacy/Security Microsystem IP/Technology Specialty DRAM De-Identification & AI+3D Vision ICs & KGDM / Innovative IPs Privacy Computing Subsystem for Robots Tera-Scale Integration IP AI+DRAM Platform to extend Moore’s Law Co-founded Companies (IPOed) USB 4.0 & Thunderbolt Controll
Slide 54: DeCloakBrain AipA Robotic System Wins 2025 COMPUTEX Golden Award
DeCloakBrain AipA Robotic System Wins 2025 COMPUTEX Best Choice Golden Award The World’s Largest AI Exhibition ! Privacy-Preserving AI Technology Dog BangBang All the personal data seen in its eyes is kept confidential. TI Autonomous Context Awareness Real-Time Anomaly Detection and Response 帝濶智慧科技股
Slide 55: Taiwan Hi-Tech Fortress Allied with Global Industries
Taiwan Hi-Tech Fortress Allied with Global Industries Contributing to IntelligenceN Eco-Systems by Semi+AI Cloud Big Data AI 5G IOT Information Communications Technology Fin Tech ML Electrical Electronic Heterogeneous Packaging Integration (HI) Server Module Microsystems Heat Dissipation IP Vertical
Slide 56: Concluding Remarks (I)
Concluding Remarks (I) Advancing 1PMLS for Immediate Demands: 2/1.8nm, 1.6/1.4nm, 1.2/1.0nm, … Pioneer 2PMLS Solutions: Addressing PPACT optimization amid accelerating paramount AI demands from Nu8, Nu5.6, Nu4.0, Nu2.8, Nu2.0, Nu1.4, Nu1.0, … In both 1PLMS & 2PLMS, Optimize Monolithic & Hetero
Slide 57: Enabling Tomorrow's AI with Heterogeneous-Technology Platform
Enabling Tomorrow’s AI with Heterogeneous-Technology Platform *LSI : Local Silicon Interconnect; eDTC: embedded Deep Trench Capacitor * IVR: Integrated Voltage Regulator Source: Yuan TSMC IEDM 2024 57
Slide 58: Concluding Remarks (II)
Concluding Remarks (II) Advancing 1PMLS for Immediate Demands: 2/1.8nm, 1.6/1.4nm, 1.2/1.0nm, … Pioneer 2PMLS Solutions: Addressing PPACT optimization amid accelerating paramount AI demands from Nu8, Nu5.6, Nu4.0, Nu2.8, Nu2.0, Nu1.4, Nu1.0, … In both 1PLMS & 2PLMS, Optimize Monolithic & Heter
Slide 59: Complementary 2D Material-based One Instruction Set Computer
A Complementary Two-dimensional Material-based One Instruction Set Computer Source: Saptarshi Das et. al, (Pennsylvania State University) “A complementary two-dimensional material-based one instruction set computer”, Nature, 2025 59
Slide 60: Study of Ultimate Limits of VDD versus Thermal Noise
Study of Ultimate Limits of VDD versus Thermal Noise 𝒌𝑻 Thermal noise : = 26mV T = 300K 𝒒 𝒌𝑻 VDDminimum : 4 x = 104 mV 𝒒 Power = CV2f : can be improved by 52X (current VDD 0.75V/0.104V)2 𝒌𝑻 Thermal noise can be further reduced at T=4K : = 0.35mV 𝒒 Power reduction can be 52 X 300/4 = 3900X…
Slide 61: Fundamental Limit on Signal Energy Transfer
A fundamental limit on signal energy transfer during an irreversible binary switching is -21 kT(ln2) ~ 2.8710 Joule@300k -24 ~ 3.8310 [email protected] k Boltzmann’s constant; T absolute temperature. Today a 10nm/3nm switching device consumes -15 -16 ~ 1E /~5E [email protected] -17 -17 ~ 2E /~1E [email protected] *
Slide 62: Global Energy Production May Meet Computing Demands (II)
Global Energy Production May Meet Ever Rising Energy Demands for Computing (II) Possible ! (Lu, 2025) Wish to Be (Lu, 2022) • AI limited Scenario * ZIPS (1021 compute * instructions per second) * * aJ: attojoule (10-18 Joules) Source: SRC, Jan 2021 (without LLM-AI) After Nicky Lu, HIR 5th Annual Con
Slide 63: From Present AI+Semi Fortress Toward Future Technologies
From Present AI+Semi Fortress Marching toward Future Technologies in Harmony of Nature & Mankind (Optimized Monolithic & Heterogeneous Integration: OMHI) Big Data AI 5G Cloud IOT Information Communications ML Technology Electrical Fin Tech Heterogeneous Electronic Integration (HI) Packaging Server M
Slide 64: Concluding Remarks (III)
Concluding Remarks (III) Advancing 1PMLS for Immediate Demands: 2/1.8nm, 1.6/1.4nm, 1.2/1.0nm, … Pioneer 2PMLS Solutions: Addressing PPACT optimization amid accelerating paramount AI demands from Nu8, Nu5.6, Nu4.0, Nu2.8, Nu2.0, Nu1.4, Nu1.0, … In both 1PLMS & 2PLMS, Optimize Monolithic & Hete
Slide 65: Symbiotic Growth of Chip+AI Industries: Lu's Perspective for 2040
Symbiotic Growth of Chip+AI Industries Lu’s Perspective for Y2040 2000 Billion$ 2000 2000 1800 Heterogeneous 1600 Integration of Silicon+Non-Silicon 1400 4.0) (Si4.0) 1200 1200 Integrated 1000 System 1000 Software Self-Smart MicroSystem Circuits ChatGPT 1000 800 (openAI) Chips (Si2.0+3.0) 600 IC Ind
Slide 66: Thank You!
Thank You! s Realize Tech Dreams ! 66