Agilent Technologies, Inc. · NYSE:A
Agilent Technologies — Technical Presentation (2005)
21 slides from Agilent Technologies's technical presentation, Mar 13, 2005
Slide 1: A 1.2GS/s 15b DAC for Precision Signal Generation
6.1: A 1.2GS/s 15b DAC for Precision Signal Generation Bob Jewett, Jacky Liu and Ken Poulton Agilent Labs, Palo Alto, CA
Slide 2: DAC Use in Direct IF for RF Instruments
DAC Use in Direct IF for RF Instruments Up- CPU & Front DAC convert Panel DSP & filter Connector • Use DSP to get complex modulation formats • Maintain instrument-class signal fidelity • Cover as wide a bandwidth as possible, up to 80% of Nyquist typically. • Cost, power, size not as important as fo
Slide 3: Goals for this DAC
Goals for this DAC • Requirements for wide-band IF generation: • At least 80MHz of bandwidth • Spurious signals < -80dBc • Signal-to-noise > 80dB in an 80MHz bandwidth • Center frequency about 300MHz or higher • Path not taken: Sigma-delta • Additional uses that require Nyquist implementation: • Arb
Slide 4: Block Diagram
Block Diagram Clocking 1200 MHz R-2R Ladder Σ Output ÷2 600MHz Resampling switches Latch Data port A 9 64 16 9 MUX LSB currents MSB currents Data port B Latch 6 VREF 16 64 Random Early/late MSB encode/DEM Data φ-det Clock Handshake • 15-bit resolution, 1200 MSample/sec, 0 dBm output power • Output i
Slide 5: Input Data Buffer
Input Data Buffer • As flexible as possible • LVDS main interface spec • Should handle ECL/PECL levels as well • Should provide on-chip terminations (50-ohm, diff) • 1200 MHz and greater receive rate Data 100 ohms to Latches PMOS Bipolar source diff-pair followers (ECL-like levels)
Slide 6: Input Data Timing Mechanism
Input Data Timing Mechanism Clock Data A,B 0 1 0 0 T 1 0 0 A-T-B sequence 0-1-1, so the data is “early” • Data and clock must be aligned at 1200 MSa/s with 100-ps accuracy (one-port mode) • A-T-B scheme from serial links techniques
Slide 7: Dynamic Element Matching
Dynamic Element Matching • In Nyquist DACs, current source mismatches can cause nonlinearities: Current source #4, large + error INL Code • If currents are chosen randomly the nonlinearities are converted into white noise: INL Code
Slide 8: MSB Current Source Randomization
MSB Current Source Randomization 8 7 / / 7 MMSBs 3-56 / 8 / encode / 3 Eight-way barrel-shifter / 7 / ... 7 8 8 / 3-8 LMSBs / encode / 3 8 Random 3 / / Random 3 / • MSB requests are binary -- convert to a unary weighted code, then scramble 64 requests • Any request may use any current source
Slide 9: Random Bit Generation
Random Bit Generation • Six random bits are needed on each cycle • Prefer to have these controlled externally • Use XORs to create other phases of the sequence: PRNGO PRB output IN FF FF FF ... FF FF for testing 1 7 2 4 5 12 XOR XOR ... XOR 6 / To DEM • Use different tap spacings to get different se
Slide 10: Global vs. Distributed Output Resampling
Global vs. Distributed Output Resampling Global: Current Resampled Data sources Σ output & switches Sample clock • Switch must be very linear for the global case Distributed: Current Resampled Data sources & switches Σ output Sample clock
Slide 11: Distributed Output Resampling
Distributed Output Resampling To R/2R To R/2R Iout Ck Ck Ck Ck } Resampling pairs Ck D D } Data pair ID VB } Current source R VREF • Data arrives first and currents go into ground • Ck switches settled current to the R/2R output • Only units currents are switched, so the process is inherently linear
Slide 12: Sin(x)/x Roll-off
Sin(x)/x Roll-off 1 NRZ output pulses 0.8 Signal amplitude 0.6 RZ output pulses 0.4 2nd Nyquist 0.2 fs/2 fs 2fs 0 0 500 1000 1500 2000 2500 Signal frequency in MHz • With a “non-return-to-zero” waveform (NRZ), the first null is at 1200MHz • With RZ (half-width pulses) there is more power at some fre
Slide 13: R/2R Ladder Design
R/2R Ladder Design R 2R 2R 2R 2R R/2R Output R R R ... R R Ck Ck ... Ck Ck D Current Resampling Switches D LSB MSB -- one of 64 • Matching to 1/4 LSB of the 9-bit ladder • Capacitance on the ladder delays the LSBs • Currents at the output can be very high, causing heating and electromigration
Slide 14: Digital Section
Resistor Array Output switches Digital Section Resistor Array 5 mm x 6 mm, 0.35-µm BiCMOS,40-GHz NPNs, 3.3V and -2V supplies, 6.5W total power
Slide 15: Test System
Test System Test board Data 64 / DAC Generator Chip Synthesizer Spectrum Analyzer Synthesizer Recording Voltmeter Workstation Oscilloscope LAN • Data generator goes up to 660/1320 MSa/s • Voltmeter has sub-LSB accuracy • Digital oscilloscope with 6GHz of bandwidth
Slide 16: Harmonic Distortion
Harmonic Distortion worst harmonic, dBc -55 -60 -65 -70 -75 1200MSa/s -80 -85 500MSa/s -90 20 40 60 80100 200 400 600 signal frequency, MHz • < -80 dBc at low frequency and clock rate • -70 dBc up to 300 MHz at 1200 MSa/s
Slide 17: Noise Spectral Density
Noise Spectral Density -146 -148 -150 noise measured at fs/4, carrier ~0dBm NSD dBc/Hz -152 small-signal case with DEM -154 -156 -158 -159dBc/Hz -160 3dB/octave -162 20 40 60 100 200 400 600 1000 2000 clock frequency, MHz • -159 dBc/Hz is 80 dB SNR in an 80 MHz BW • The chip clocks to beyond 2000 MH
Slide 18: Integral Nonlinearity (INL)
Integral Nonlinearity (INL) 6 INL (LSBs) 0 without DEM -6 8 INL (LSBs) 4 with DEM 0 -4 -8 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 Code (/full scale) • DEM reduces DNL 3x but adds 3rd-order distortion • May be from transients in the current sources
Slide 19: Two-Tone IMD vs. Frequency
Two-Tone IMD vs. Frequency -72 Full scale 0dBm @ 300MHz -74 Each carrier -6dBfs IMD dBc -76 -78 -80 -82 -84 80 100 200 300 400 500 600 Signal pair frequency (MHz)
Slide 20: Adjacent Channel Power Ratio (ACPR)
Adjacent Channel Power Ratio (ACPR) 4-Channel W-CDMA, 20MHz BW Signal power Noise + disto. power • At 300 MHz, ACPR is -72 dBc • At 900 MHz, ACPR is -69 dBc • RZ for better high-frequency performance
Slide 21: Summary
Summary • 1200 MSa/s spec’ed, operation to 2000 MSa/s • -69 dB ACPR in 2nd Nyquist band (900 MHz) • Distributed resampling improves performance by 6 dB • Dynamic element matching improves DNL