Arteris, Inc. · NASDAQ:AIP
Arteris — Technical Presentation (June 2026)
21 slides from Arteris's technical presentation, June 2026
Slide 1: Scalable Coherent Multi-Die Solutions for AI, HPC, and Automotive ADAS
Scalable Coherent Multi-Die Solutions for AI, HPC, and Automotive ADAS Ashley Stevens and Bhavana Dhara June 2026 1 © 2026 Arteris, Inc. All rights reserved.
Slide 2: Chiplets Enable AI Compute Growth at 'More than Moore' Speed
Chiplets Enable AI Compute Growth at ‘More than Moore’ Speed Moore’s Law: Coming to an End AI Compute Era: Previously doubling every 2 years Doubling in <4 months! PETAFLOPS / S-DAYS Node Shrink More Compute 2 © 2026 Arteris, Inc. All rights reserved.
Slide 3: The Multi-Die Paradigm Shift
The Multi-Die Paradigm Shift The Chiplet Revolution Enables: Scalability – To larger than a single die Cost – Reduced costs with multiple smaller dies Portfolio of products – Mix and match dies to differentiate products Ecosystem – Multi-vendor interoperability 3 © 2026 Arteris, Inc. All rights rese
Slide 4: Network-on-Chip (NoC) SoC Interconnect IPs
Network-on-Chip (NoC) SoC Interconnect IPs Networking techniques for improved on-chip communication & data flow Smaller Lower Power Faster Frequency Shorter, Predictable Rapid Timing Automated Easy Die Area Consumption Lower Latency Schedules Closure Estimation Verification Configuration CPU Subsyst
Slide 5: Multi-Die Extends Coherency Across Dies
Ncore Multi-Die Extends Coherency Across Dies Die 1 Die 2 GPU CPU CPU CPU CPU GPU CAIU CAIU CAIU CAIU CXS GIU CXS UCIe UCIe GIU UCIe UCIe FlexGen / FlexGen / FlexNoC FlexNoC Ctrl PHY PHY Ctrl Ncore Ncore ISP ISP DII DII UCIe UCIe GIU CXS UCIe UCIe CXS GIU Ctrl PHY PHY Ctrl DMI NCAIU DMI NCAIU Memory
Slide 6: Multi-Die Assemblies
Multi-Die Assemblies An ‘Assembly’ is a configuration of dies, either homogeneous or heterogeneous Homogeneous Coherent Chiplets Heterogeneous Coherent Chiplets (Multiple instance of the same chiplet) (Chip disaggregation) Fully Connected Mesh Triple Dual 1 2 1 2 3 1 1 1 1 1 1 1 2 Single 1 1 1 1 1 1
Slide 7: Multiple Multi-Die Assemblies
Multiple Multi-Die Assemblies An ‘Assembly’ is a configuration of dies, either homogeneous or heterogeneous Homogeneous Coherent Chiplets Heterogeneous Coherent Chiplets (Multiple instance of the same chiplet) (Chip disaggregation) Fully Connected Mesh Triple Dual 1 2 1 2 3 1 1 1 1 1 1 1 2 Single 1
Slide 8: Multi-Die Per-Link Throughput
Multi-Die Per-Link Throughput UCIe 1.1 Standard 32GB/s peak bandwidth Organic Interposer CXS.B GIU Interface 512 bits @ 500MHz 16GB/s usable – protocol and 16 lanes, 16GT/s packetization Up to 4 links can be interleaved for increased point-to-point bandwidth UCIe 1.1 Advanced CXS.B GIU Interface 128
Slide 9: Network Interface to GIU
Network Interface to GIU 256→512 256→512 VC VC NoC De- NoC NoC De- NoC 256→512 512b packetizer 512 256b packetizer 256→512 CXS.B 256→512 512b GIU CXS.B GIU 256512 512 VC 512b 256512 VC NoC NoC NoC NoC 256512 Packetizer Packetizer 256b 256512 256512 UCIe Standard UCIe Advanced Network solution c
Slide 10: Pin Swapping for Die Rotation by the UCIe PHY
Pin Swapping for Die Rotation by the UCIe PHY P P GIU0 H GIU0 H Y Y Pin swapping handled in UCIe PHY 10 © 2026 Arteris, Inc. All rights reserved.
Slide 11: Programmable Routing Simplifies Chiplet Rotation
Programmable Routing Simplifies Chiplet Rotation GIU0 GIU0 GIU1 GIU1 GIU2 GIU2 GIU3 GIU3 ▪ Programmable routing enables routing to any GIU. ▪ Port swapping handled by Arteris Ncore interconnect. ▪ Pin swapping handled by UCIe PHY. 11 © 2026 Arteris, Inc. All rights reserved.
Slide 12: Chiplet Network Routing: Mesh
Mesh Chiplet Network Routing 1 1 Mesh routing is X-Y to avoid deadlock 1 1 ▪ Chiplet assemblies are either a mesh or fully-connected A B ▪ Routing split into two independent tasks: – Global routing, die-to-die to next chiplet – Local routing, on die to destination unit, or GIU to remote die – Hierar
Slide 13: Chiplet Network Routing: Fully Connected
Fully Connected Chiplet Network Routing 1 1 Fully-connected routing is lower latency 1 1 ▪ Chiplet assemblies are either a mesh or fully-connected A B – Lower latency with fully-connected ▪ Fully-connected routing is lower latency ▪ Response is always point-to-point C D – 2 global hops vs 4 global h
Slide 14: Hierarchical Address Map
Chiplet 2 Hierarchical Address Map Addr Size Dest. ▪ Each chiplet has its own address map A000 8kB DMI1 – Defines either a local destination or a remote chiplet GIU0 8000 8kB DMI0 GIU1 ▪ Address is decoded every time it crosses a chiplet boundary 4000 16kB Chiplet1 – Local destination will have lowe
Slide 15: Extending Functional Safety to Multi-Die Designs
Extending Functional Safety to Multi-Die Designs ▪ ASIL level selected in tooling and automatically applied to Ncore ▪ Homogeneous ASIL level over assembly – Ncore ASIL level is the same for each die Duplicate Fault ▪ GIU duplication with delay and checker GIU status ▪ End-to-end protection of trans
Slide 16: Lookback for Multi-Die Debug
Lookback for Multi-Die Debug UCIe UCIe GIU Ncore CXS.B CXS.B UCIE Ncore CXS.B CXS.B GIU Local loopback Remote loopback ▪ Within the GIU ▪ In the 3rd party UCIe controller ▪ In the 3rd remote party Controller - Before the transceiver - After the transceiver 16 © 2026 Arteris, Inc. All rights reserved
Slide 17: Multi-Die Configuration Demo
Multi-Die Configuration Demo 17 © 2026 Arteris, Inc. All rights reserved.
Slide 18: Multi-Die Tooling Outputs
Multi-Die Tooling Outputs Aggregated Assembly CSR Documentation PDF Assembly Documentation HTML Assembly Documentation 18 © 2026 Arteris, Inc. All rights reserved.
Slide 19: Multi-Die Integration Automation with Magillem Platform
Multi-Die Integration Automation with Magillem Platform IP IP IP Magillem Connectivity Magillem Registers Easy Port, parameter, bus interface, Memory map, bridge definition Configuration source files(fileset) Import and IP Packaging IP Chiplet Assembly IP HW/SW Interface Continuous IP (Capture, edit
Slide 20: Arteris Multi-Die Solution
Arteris Multi-Die Solution Delivers foundational technology for rapid chiplet-based innovation across all markets Benefits from adopting chiplet technology ▪ Enables greater scalability for current and future designs. ▪ Enables greater flexibility for creating a range of devices. ▪ Our tooling-based
Slide 21: Thank you
Thank you Get a copy of our multi-die solution brief to explore the topic further: https://www.arteris.com/trademarks Arteris, Inc. All rights reserved worldwide. Arteris, Arteris IP, the Arteris IP logo, and the other Arteris marks found at https://www.arteris.com/trademarks are trademarks or regis