Analog Devices, Inc. · NASDAQ:ADI
Analog Devices — Technical Presentation (December 2008)
49 slides from Analog Devices's technical presentation, December 2008
Slide 1: Core Architecture Overview
The World Leader in High Performance Signal Processing Solutions Core Architecture Overview Presented by: George Kadziolka President Kaztek Systems
Slide 2: About This Module
About This Module This module introduces the Blackfin® family and provides an overview of the Blackfin processor architecture. 2 Core Architecture Overview
Slide 3: Module Outline
Module Outline Blackfin Family Overview The Blackfin Core • Arithmetic operations • Data fetching • Sequencing The Blackfin Bus Architecture and Memory • Modified Harvard architecture • Hierarchical memory structure • Flexible memory management Additional Blackfin Core Features • DMA • Dynamic power
Slide 4: Blackfin Family Overview
Blackfin Family Overview The Blackfin family consists of: • A broad range of Blackfin processors • Software development tools • Hardware evaluation and debug tools Extensive third-party support • Development tools • Operating systems • TCP/IP stacks • Hardware building blocks • Software solutions 4
Slide 5: Blackfin Processors
Blackfin Processors All Blackfin processors combine extensive DSP capability with high end MCU functions on the same core. • Creates a highly efficient and cost-effective solution. • A single software development tool chain All Blackfin processors are based on the same core architecture. • Once you
Slide 6: Blackfin Family Peripherals
Blackfin Family Peripherals The Blackfin family supports a wide variety of I/O: • EBIU (External Bus Interface Unit) • Parallel peripheral interface (PPI) • Serial ports (SPORTS) • GPIO • Timers • UARTS • SPI® • Ethernet • USB • CAN® • Two Wire Interface (TWI) • Pixel compositor • Lockbox™ secure te
Slide 7: Blackfin Processors Perform Signal Processing and Microcontroller Functions
Blackfin Processors Perform Signal Processing and Microcontroller Functions Traditional Model MCU ASIC • Control Signal Processing • Interfaces to sensors • Networking • Broad peripheral mix • RTC • Memory MCU Signal Processing ASIC • Watchdog • RTOS Signal Processing • MMU • Byte addressable New Mo
Slide 8: Blackfin Architecture: What does it mean for the developer?
Blackfin Architecture What does it mean for the developer? Combining controller and DSP capabilities into a single core, along with rich I/O, enables development of efficient, low cost embedded media applications. • For example, multimedia over IP, digital cameras, telematics, software radio From a
Slide 9: Features
Features Controller •L1 memory space for stack and heap •Dedicated stack and frame pointers •Byte addressability •Simple bit-level manipulation DSP • Fast, flexible arithmetic computational units • Unconstrained data flow to/from computational units • Extended precision and dynamic range • Efficient
Slide 10: Blackfin Core (e.g., ADSP-BF54x)
Blackfin Core (e.g., ADSP-BF54x) 10 Core Architecture Overview
Slide 11: The Blackfin Core
The Blackfin Core 11 Core Architecture Overview
Slide 12: The Blackfin Core
The Blackfin Core The core consists of: Arithmetic unit • Supports SIMD operation • Load/store architecture Addressing unit • Supports dual data fetch Sequencer • Efficient program flow control Register files • Data • Addressing 12 Core Architecture Overview
Slide 13: The Arithmetic Unit
The Arithmetic Unit Performs arithmetic operations Dual 40-bit ALU (Arithmetic/ Logic Unit) • Performs 16-/32-/40-bit arithmetic and logical operations Dual 16 x 16 multiplier • Performs dual MACs (multiply-accumulates) when used with ALUs Barrel shifter • Performs shifts, rotates, bit operations 13
Slide 14: Data Registers
Data Registers There are 8x 32-bit registers in the data register file. • Used to hold 32-bit vales or packed 16-bit There are also 2x 40-bit accumulators. • Typically used for MAC operations Data Registers 39 31 15 0 A0.X A0.H A0.L A1.X A1.H A1.L 31 15 0 R0 R0.H R0.L R1 R1.H R1.L R2 R3 R4 R4.H R4.L
Slide 15: 16-Bit ALU Operations—Examples
16-Bit ALU Operations—Examples The Algebraic Assembly syntax is intuitive and makes it easy to understand what the instruction is doing. Single 16-bit operation Dual 16-bit operation Quad 16-bit operation R6.H = R3.H + R2.L (s); R6 = R2 + | - R3; R3 = R0 - | - R1, R2 = R0 + | + R1; 31 16 0 31 16 0 3
Slide 16: 32-Bit ALU Operations—Examples
32-Bit ALU Operations—Examples Single 32-bit addition Dual 32-bit operation R6 = R2 + R3; R3 = R1 - R2, R4 = R1 + R2; 31 0 31 0 31 0 R2 R1 R1 R3 R2 R2 + - + R6 R4 R3 These operations effectively execute in a single cycle. 16 Core Architecture Overview
Slide 17: Dual MAC Operations—Example
Dual MAC Operations—Example Both MACs can be used at the same time to double the MAC throughput. The same two 32-bit input registers must be used (R2 and R3 in this example). Dual MAC operation R2 R3 x x - + A0 A1 A1 -= R2.H * R3.H, A0 += R2.L * R3.L; These operations effectively execute in a single
Slide 18: Barrel Shifter
Barrel Shifter Enable shifting or rotating any number of bits within a 16-/32-/40-bit register in a single cycle Perform individual bit operations on 32-bit data register contents • BITSET, BITCLR, BITTGL, BITTST Field Extract and Deposit instructions • Extract or insert a field of bits out of or in
Slide 19: 8-Bit Video ALUs
8-Bit Video ALUs Four Video ALUs 19 Core Architecture Overview
Slide 20: 8-Bit ALU Operations
8-Bit ALU Operations Four 8-bit ALUs provide parallel computational power targeted mainly for video operations. • Quad 8-bit add/subtract • Quad 8-bit average • SAA (Subtract-Absolute-Accumulate) instruction A quad 8-bit ALU instruction takes one cycle to complete. 64-Bit/8-Byte Field 64-Bit/8-Byte
Slide 21: Additional Arithmetic Instructions
Additional Arithmetic Instructions There are a number of specialized instructions that are used to speed up the inner loop on various algorithms. Bitwise XOR • Enable creating LFSR (Linear Feedback Shift Registers) for use in CRC calculations or the generation of PRN sequences Bit stream multiplexin
Slide 22: The Addressing Unit
The Addressing Unit The addressing unit generates addresses for data fetches. •Two DAG (Data Address Generator) arithmetic units enable generation of independent 32-bit wide addresses that can reach anywhere within the Blackfin memory space. •Up to two fetches can occur at the same time. 22 Core Arc
Slide 23: Address Registers
Address Registers There are 6x general-purpose Pointer Registers. 31 0 • Used for GP 8-/16-/32-bit fetches P0 Address from memory Registers P1 Pointer Registers: There are four sets of registers used P2 P0-P5 are referred to as “preg.” for DSP-style data accesses. P3 P4 • Used for 16-/32-bit DSP dat
Slide 24: Addressing
Addressing Addressing Unit supports: • Addressing only • With specified Pointer or Index Register • Provide address and post modify • Add an offset after the fetch is done • Circular buffering supported with this method • Provide address with an offset • Add an offset before the fetch, but no pointe
Slide 25: Circular Buffer Example
Circular Buffer Example Example Address Base address (B) and 0x00 0x00000001 1st Access 0x00000001 Starting address (I) = 0 0x00000002 0x00000002 0x04 4th Access Buffer length 0x08 0x00000003 0x00000003 L = 44 0x0C 0x00000004 0x00000004 (There are 11 data elements and each data element is 0x10 0x000
Slide 26: The Sequencer
The Sequencer The sequencer’s function is to generate addresses for fetching instructions. • Uses a variety of registers to select the next address Aligns instructions as they are fetched • Always reads 64 bits from memory • Realigns what is fetched into individual 16-/32-/64-bit opcodes before send
Slide 27: Program Flow
Program Flow 27 Core Architecture Overview
Slide 28: Sequencer Registers
Sequencer Registers These are registers that are used in the control of program flow. Arithmetic Status (ASTAT) tracks status bits for core operations. • Used in conditional execution of instructions. Return address registers. • Hold the 32-bit return address for program flow interruptions. Two sets
Slide 29: Instruction Pipeline
Instruction Pipeline The pipeline is fully interlocked. In the event of a data hazard, the sequencer automatically inserts stall cycles. Pipeline Stage Description Issue instruction address to IAB bus, start compare Instruction Fetch 1 (IF1) tag of instruction cache Instruction Fetch 2 (IF2) Wait fo
Slide 30: Instruction Pipeline
Instruction Pipeline IF1 IF2 IF3 DEC AC DF1 DF2 EX1 EX2 WB Cycle N INST #1 N+1 INST #2 INST #1 N+2 INST #3 INST #2 INST #1 N+3 INST #4 INST #3 INST #2 INST #1 N+4 INST #5 INST #4 INST #3 INST #2 INST #1 N+5 INST #6 INST #5 INST #4 INST #3 INST #2 INST #1 N+6 INST #7 INST #6 INST #5 INST #4 INST #3 I
Slide 31: Blackfin Event Handling
Blackfin Event Handling Blackfin events include: • Interrupts • Generated by hardware (e.g., DMA complete) or software • Exceptions • Error condition or service related Handling is split between the CEC (Core Event Controller) and SIC (System Interrupt Controller). • CEC has 16 levels and deals with
Slide 32: System and Core Interrupts (ADSP-BF533 example)
System and Core Interrupts (ADSP-BF533 example) System Interrupt Source IVG #1 Core Event PLL Wakeup interrupt IVG7 Event Source IVG # Name DMA error (generic) IVG7 Highest Emulator 0 EMU PPI error interrupt IVG7 SPORT0 error interrupt IVG7 Reset 1 RST SPORT1 error interrupt IVG7 Non Maskable Interr
Slide 33: Variable Instruction Lengths
Variable Instruction Lengths The Blackfin architecture uses three instruction opcode lengths to obtain the best code density while maintaining high performance. 16-bit instructions • Most control-type instructions and data fetches are 16-bits long to improve code density. 32-bit instructions • Most
Slide 34: Instruction Packing
Instruction Packing When code is compiled and linked, 16-bit OP 32-bit OP the instructions are packed into 64-bit Multi-OP memory as densely as possible. Instruction Formats • i.e., no wasted memory space 15 0 No memory alignment restrictions for code: • Instructions can be placed anywhere in memory
Slide 35: 16-bit FIR Filter Example—0.5 cycles per tap
16-bit FIR Filter Example—0.5 cycles per tap 31 0 Input Input R0 Input data delay line Coefficients Coefficient Coefficient R1 MAC into A0 MAC1 MAC0 R0L x0 x0 R1L A1 into M AC x x R0H x1 MAC into A0 to A 1 x1 R1H AC in + + A0 R0L x2 M x2 R1L x3 x3 R1H R0H A1 39 0 Loop: A1+=R0.H*R1.L, A0+=R0.L*R1.L |
Slide 36: Bus and Memory Architecture
Bus and Memory Architecture 36 Core Architecture Overview
Slide 37: Blackfin Memory Hierarchy
Blackfin Memory Hierarchy The Blackfin architecture uses a memory hierarchy with a primary goal of achieving memory performance similar to that of the fastest memory (i.e., L1) with an overall cost close to that of the least expensive memory (i.e., L3). • Portions of L1 can be configured as cache, w
Slide 38: Internal Bus Structure of the ADSP-BF533
Internal Bus Structure of the ADSP-BF533 38 Core Architecture Overview
Slide 39: Configurable Memory
Configurable Memory The best system performance can be achieved when executing code or fetching data out of L1 memory. Two methods can be used to fill the L1 memory—caching and dynamic downloading–the Blackfin processor supports both. • Microcontrollers have typically used the caching method, as the
Slide 40: Cache and Memory Management
Cache and Memory Management Cache allows users to take advantage of single-cycle memory without having to specifically move instructions and or data “manually.” • L2/L3 memory can be used to hold large programs and data sets. • The paths to and from L1 memory are optimized to perform with cache enab
Slide 41: Additional Blackfin Core Features
Additional Blackfin Core Features 41 Core Architecture Overview
Slide 42: Direct Memory Access (DMA)
Direct Memory Access (DMA) The Blackfin processors includes a DMA (Direct Memory Access) facility on all CPUs. • Enable moving data between memory and a peripheral, or memory to memory without using any core cycles • Core only involved in setting up DMA parameters • Core is interrupted when DMA comp
Slide 43: Power Management Options
Power Management Options Low active power • Flexible power management with automatic power-down for unused peripheral sections. • Dynamic power management allows dynamic modification of both frequency and voltage. • PLL can multiply CLKIN from 1x to 64x. • Core voltage can be optimized for the opera
Slide 44: Blackfin Processors Optimize Power Consumption
Blackfin Processors Optimize Power Consumption Vdd 1.2V, 500 MHz Processor Operation t 0.9V, 250 MHz PLL Processor Operation Settling 0.8V, 100 MHz PLL Regulator Settling Processor Operation Regulator Power Transition Transition Consumption Just varying the frequency mW Dynamic Power Management Vary
Slide 45: Power Mode Transitions
Power Mode Transitions Under software control, the application can change from one power state to another. A set of libraries (i.e., System Services) enable control of clocking, core voltage, and power states with just a function call. 45 Core Architecture Overview
Slide 46: Hardware Debug Support
Hardware Debug Support 46 Core Architecture Overview
Slide 47: Advanced Support for Embedded Debug
Advanced Support for Embedded Debug The JTAG port is also used to provide in-circuit emulation capabilities. • Nonintrusive debugging • BTC (background telemetry channel) Hardware breakpoints • Six instruction and two data watchpoints Performance monitor unit • Counters for cycles and occurrences of
Slide 48: Summary
Summary The Blackfin core has a number of features and instructions that support both control and DSP types of operations. The Blackfin’s high performance memory/bus architecture supports zero wait state instruction and dual fetches from L1 at the core clock rate, all at the same time. • Large appli
Slide 49: Resources
Resources For detailed information on the Blackfin architecture, please refer to the Analog Devices website which has links to manuals, data sheets, FAQs, Knowledge Base, sample code, development tools and much more: • www.analog.com/blackfin For specific questions click on the “Ask a question” butt
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