Asml Holding Nv · EURONEXT:ASML

Asml Holding Nv — Investor Day (November 2014)

17 slides from Asml Holding Nv's investor day presentation, Nov 24, 2014

1. Slide 1: Holistic Lithography

   Holistic Lithography Christophe Fouquet Executive Vice President, Applications 24 November 2014

2. Slide 2: Holistic Lithography – Introduction

   Holistic Lithography – Introduction Public Slide 3 Customer Problem: November 2014 • Beyond 20nm node scanner and non scanner contributions must be addressed to meet patterning performance requirements ASML Holistic Lithography: • ASML provides a unique and comprehensive holistic capability via inte

3. Slide 3: Customer problem: scanner and non scanner contributors to patterning performance

   Customer problem: scanner and non scanner contributors to patterning performance must be addressed – example Overlay Public Slide 4 November 2014 Scanner Overlay Error Contribution Other Overlay Error Contributors wafer 7 ovX ovY 99.7 42.1 43.8 Max 42.1 43.8 10 nm m+3s 60.1 69.7 XYSMO_DCOSAT1_201404

4. Slide 4: ASML holistic lithography: links scanner to YieldStar metrology and computational lithography

   ASML holistic lithography: links the scanner to YieldStar Public metrology and computational lithography design context Slide 5 November 2014 NXT - Immersion NXE - EUV 1.Advanced lithography capability 4. Process Window Enlargement 5. Process Window Control 2- YieldStar 3- Computational Metrology an

5. Slide 5: Why ASML?: Scanner is the only tool controlling the wafer at field level

   Why ASML?: Scanner is the only tool processing and Public controlling the wafer at field level Slide 6 November 2014

6. Slide 6: Why ASML?: Multiple scanner knobs enable in-line optimization

   Why ASML?: Multiple scanner knobs enable in-line Public optimization of patterning performance Slide 7 November 2014 FlexRay illuminator I FlexRay illuminator Illumination D Even Fingers Dose Odd Fingers Grey Filter Interfaces (knobs) Optical Centerline manipulator Y Dose actuators X Z O Reticle sta

7. Slide 7: Customer benefits: Adoption of holistic lithography at 20nm node

   Customer benefits: Adoption of holistic lithography at 20nm node enables customers to meet patterning requirements Public Slide 8 November 2014 Other overlay Scanner overlay contribution contribution 8 L28 28nm node Overlay Requirement 7 X On product overlay 6 Rework & Yield 5 L20 20nm node Overlay

8. Slide 8: Increasing customer engagements

   ASML is working intimately with its customers to deliver Public patterning requirement through our expert support Slide 9 November 2014 Customer Technology Nodes 2010 2011 2012 2013 2014 2015 2016 2017 Customer A O F O CD O F CD O F CD Node Transition 0x Customer B Customer Engagements O O F O F D N

9. Slide 9: ASML will build holistic lithography infrastructure over the next 5 years (1)

   ASML will build and implement holistic lithography Public infrastructure over the next 5 years Slide 10 November 2014 Ramp 1 2012 2013 2014 2015 2016 2017 2018 2019 2020 Volume Standalone YieldStar Test wafers Scanner stable +- 1nm over 12 months Overlay, Focus Scanner OVL stability (Low frequency,

10. Slide 10: ASML will build holistic lithography infrastructure over the next 5 years (2)

    ASML will build and implement holistic lithography Public infrastructure over the next 5 years Slide 11 November 2014 Ramp 2 2012 2013 2014 2015 2016 2017 2018 2019 2020 Volume Standalone Integrated YieldStar YieldStar Test wafers Product wafers Overlay, Focus Overlay, Focus &CD after Lithography (L

11. Slide 11: ASML will build holistic lithography infrastructure over the next 5 years (3)

    ASML will build and implement holistic lithography Public Slide 12 infrastructure over the next 5 years November 2014 Ramp Next 2012 2013 2014 2015 2016 2017 2018 2019 2020 Volume Standalone Integrated YieldStar Standalone YieldStar YieldStar ETCH Test wafers Product wafers Overlay, Focus Overlay, F

12. Slide 12: BRION computational lithography continues to extend process window

    So far: BRION computational lithography continues to Public extend process window, also using scanners interfaces Slide 13 November 2014

13. Slide 13: Computational lithography enters wafer fab to provide design context to metrology

    Now: Computational lithography enters wafer fab to provide design context to metrology… Public Slide 14 November 2014

14. Slide 14: Control software – Process window optimization

    … and control software – Process window optimization Public With subsequent SEM based verification and Scanner focus optimization Slide 15 November 2014 Simulated & through SMO Measured actual product Patterning defect map Defect Focus optimization optimized die based Process wafer Defocus Map predi

15. Slide 15: Good prospects: Process Window Optimization capturing more defects

    Good prospects Process Window Optimization Public Capturing more defects vs. POR Inspection as verified by SEM Slide 16 November 2014 100 Capture Rate (%) 80 60 PWO 40 20 0 100 Nuisance Rate (%) 80 60 PWO 40 20 0 Feature type evaluated

16. Slide 16: ASML holistic lithography: links scanner to YieldStar metrology and computational lithography

    ASML holistic lithography: links the scanner to YieldStar Public metrology and computational lithography design context Slide 17 November 2014 Scanner performance with control knobs & interfaces to enable correction of errors outside of scanner NXT - Immersion NXE - EUV Metrology provides Modeling c

17. Slide 17: Public Slide 18 November 2014

    Public Slide 18 November 2014

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