Asml Holding Nv · EURONEXT:ASML
Asml Holding Nv — 2013 SPIE Advanced Lithography
50 slides from Asml Holding Nv's conference presentation, Feb 28, 2013
Slide 1: ASML's NXE platform performance and volume introduction
ASML’s NXE platform performance and volume introduction Rudy Peeters 2013 SPIE Advanced Lithography, San Jose CA, 8679-50
Slide 2: Industry roadmap towards < 10 nm resolution
Industry roadmap towards < 10 nm resolution Public Lithography supports shrink roadmap Slide 2 Trick: 200 KrF Logic / SRAM Logic 14.1% NAND 17% DRAM 13.9% Resolution / half pitch, "Shrink" [nm] 100 ArF 80 6 Transistor AT:1200 SRAM Cell ArFi 60 k1 0.40 ~ 0.44 XT:1400 50 XT:1700i 40 XT:1900i DPT NXT:1
Slide 3: NXE technology roadmap has great extendibility
NXE technology roadmap has great extendibility Public Slide 3 Under study Resolution [nm] 32 27 22 16 13 10 7 <7 Wavelength [nm] layo13.5 0.25 0.33 0.33NA DPT 0.45-0.60 DPT Lens NA ut 0.45 0.60 flare 8% 6% 4% coherence s=0.5 s=0.8 s=0.2-0.9 Flex-OAI Extended Flex-OAI Illumination reduced pupil fill
Slide 4: ASML's NXE:3100 and NXE:3300B
ASML’s NXE:3100 and NXE:3300B Public Slide 4 NXE:3100 NXE:3300B NA 0.25 0.33 Illumination Conventional 0.8 s Conventional 0.9 s Off-axis illumination Resolution 27 nm 22 nm Dedicated Chuck Overlay / 4.0 nm / 7.0 nm 3.0 nm / 5.0 nm Matched Maching Overlay Productivity 6 - 60 Wafers / hour 50 - 125 Wa
Slide 5: Contents
Public Slide 5 Contents NXE:3100 Productivity Overlay Imaging NXE:3300B Summary and acknowledgements
Slide 6: The NXE:3100 has exposed >30,000 wafers
The NXE:3100 has exposed >30,000 wafers Enabling customers to go through cycles of learning Public Slide 6 35000 30000 Total wafers exposed on NXE:3100 25000 20000 15000 10000 5000 0 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 2010 2011 2012
Slide 7: Good overlay on NXE:3100 at customers
Good overlay on NXE:3100 at customers Public Slide 7
Slide 8: And consistent good overlay for all NXE:3100 tools
And consistent good overlay for all NXE:3100 tools Public Matched Machine Overlay ~6 nm Slide 8 10.0 10.0 10.0 10.0 10.0 10.0 A B C D E F 8.0 8.0 8.0 8.0 8.0 8.0 6.0 6.0 6.0 6.0 6.0 6.0 4.0 4.0 4.0 4.0 4.0 4.0 2.0 2.0 2.0 2.0 2.0 2.0 0.0 0.0 0.0 0.0 0.0 0.0 Overlay X-axis All numbers are (X,Y) match
Slide 9: Large process windows measured on the NXE:3100
Large process windows measured on the NXE:3100 Down to 14 nm node SRAM M1 layer Public Slide 9 EUV: EUV: ArFi: 14 nm node 20 nm node 20 nm node Single exposure Single exposure Double exposure 20 nm node ArFi 20 nm node EUV 55 14 nm node EUV 50 45 CD [nm] 40 35 30 25 -200 -150 -100 -50 0 50 100 150 2
Slide 10: Dense CH imaging down to 26 nm on NXE:3100
Dense CH imaging down to 26 nm on NXE:3100 Public Slide 10 ArFi NXT:1950i NA=1.35 55 nm CHs 40 nm CHs Single exposure, Double dipole quasar exposure Positive tone Negative tone developer developer EUV NXE:3100 NA=0.25 40 nm CHs 26 nm CHs Single Exposure Single Exposure (Conventional) (Quasar) 55 nm
Slide 11: Customer NXE:3100 CDU result
Customer NXE:3100 CDU result Public Slide 11
Slide 12: Contents
Public Slide 12 Contents NXE:3100 NXE:3300B status Overview Productivity Defectivity Overlay Imaging Summary and acknowledgements
Slide 13: Eleven NXE:3300B systems in various states of integration
Eleven NXE:3300B systems in various states of integration new clean room completely finalized in July ‘12 Public Slide 13 System 1 System 9 Development tool System 2 New cleanroom System 6 System 3 System 7 System 4 System 8 System 5 System 10 Training
Slide 14: Contents
Public Slide 14 Contents NXE:3100 NXE:3300B status Overview Productivity Defectivity Overlay Imaging Summary and acknowledgements
Slide 15: ~450,000 wafers cycled on NXE:3300B for integration and reliability testing
~450,000 wafer cycled on NXE:3300B for integration and reliability testing Public Slide 15 500000 Accumulated number of wafers cycled 450000 ~450kwafers cycled on NXE:3300B scanner 400000 systems at high scan speeds for accelerating 350000 reliability testing 300000 (current MTBI (mean time between
Slide 16: Stage dynamics performance demonstrated up to 100 wafers per hour
Stages dynamics performance demonstrated up to 100 wafers per hour Public Slide 16 100 wafers per Hour NXE 3300B unit Required results Move parameters Step velocity [m/s] 1 1 Scan velocity expose [m/s] 0.25 0.25 Scan acceleration expose x/y [m/s2] 35/25 35/25 Scan velocity measure [m/s] 1 1 Jerk x/y
Slide 17: EUV source system cross-section
EUV source system cross-section Public Slide 17 Vessel Scanner Droplet EUV&droplet Generator Metrology Intermediate CO2-droplet Metrology Focus Unit Main Pulse / Pre Pulse split Focusing Collector Plasma+Energy Key components: Control metrology for Machine Control z source to x scanner • Drive Laser
Slide 18: MOPA PrePulse Technology Validated with Power, Dose Stability and Collector Protection
MOPA PrePulse Technology Validated with Power, Public Dose Stability and Collector Protection Slide 18 Power Dose Control Availability Comment 40W 99.99% of dies <0.2% dose repro, Proven Collector Protection six 1-hour runs during 8.5 100% duty cycle within die exposure and at settings hours of oper
Slide 19: 40W stable dose control performance for six 1-hour runs
40W stable dose control performance for six 1-hours Public for MOPA-PrePulse Slide 19 41 Power [W] 40.5 Data taken under demonstrated collector protection conditions 40 39.5 39 50 100 150 200 250 300 350 400 450 500 1 Time [min] Dose Error [%] 0.5 0 -0.5 -1 0 50 100 150 200 250 300 350 400 450 500 T
Slide 20: 55W EUV Power Demonstrated using MOPA Prepulse
55W EUV Power Demonstrated using MOPA Prepulse Public Slide 20 Good dose control and under collector protection conditions 60 50 40 Power [W] In die dose 30 55W EUV Power variation 1 hour run 20 10 0 10 20 30 40 50 60 Time [min] 55W EUV Power with 97.5% die yield Presentation: David Brandt (Cymer)
Slide 21: EUV Source Power Progress reaching 55 W
EUV Source Power Progress reaching 55 W Public Supporting 43 Wafers/hr, 250 W target to be reached in 2015 Slide 21 40 At 55 W, 1 run: 97.5% of the dies < 0.5% dose At 40 W, 6 runs: 99.99 of the dies < 0.2% dose, 7 one hour runs total representing ~ 250 exposed wafers @ 15 mJ/cm2
Slide 22: Contents
Public Slide 22 Contents NXE:3100 NXE:3300B status Overview Productivity Defectivity Overlay Imaging Summary and acknowledgements
Slide 23: The mask defect challenge
The mask defect challenge Public Challenging defect requirements on reflective pellicle less EUV mask Slide 23 DUV Reticles EUV Reticles (193nm) (13.5nm) Reflective multilayer Reticle Reticle Absorber Pellicle pattern Transmitted Particle (nm size) illumination Particle (mm size) Reflected illuminat
Slide 24: Substantial progress defect-free mask handling
Substantial progress defect-free mask handling Public pellicle would reduce defect requirements orders of magnitude Slide 24 Added particles > 92 nm per reticle pass Required for full EUV Reticles 100 production with pellicle ~10x / year (over the past few (13.5nm) years) progress achieved on ASML @
Slide 25: NXE:3300B particles per reticle pass performance
NXE:3300B particles per reticle pass performance Public <0.02 on multiple systems Per PRP test 15 wafers cycled Slide 25 0.500 Particles per Reticle Pass (PRP) ≥92nm 0.450 System A System B System C System D 0.400 Procedural Learning 0.350 Now cleaning ongoing 0.300 0.250 0.200 0.150 0.100 0.050 0.0
Slide 26: EUV pellicle considered as backup with minimum transmission and imaging loss
EUV pellicle considered as backup with minimum Public transmission and imaging loss Slide 26 EUV Reticles 25-nm thick (13.5nm) Reflective ᶲ 80 mm multilayer Reticle Absorber pattern Pellicle • Requirement: 90% transmission, Particle (mm size) Reflected 114x142 mm² illumination • Status: 87% transmis
Slide 27: Contents
Public Slide 27 Contents NXE:3100 NXE:3300B status Overview Productivity Defectivity Overlay Imaging Summary and acknowledgements
Slide 28: Customer On-Product-Overlay roadmap
Customer On-Product-Overlay roadmap Public Slide 28 ASML assessment based on customer inputs
Slide 29: NXE:3300B overlay improvements
NXE:3300B overlay improvements Better wafer load grid performance and improved wafer clamp flatness Public Slide 29 ADT NXE:3100 NXE:3300B Clamping NCE. Wafer run 3 of 5 Improved wafer load grid performance (S2N) Measured by repeatedly clamping a wafer 3 nm 20-5nm 99.7% x: 4.4 nm y: 5.1 nm 2nm 100%
Slide 30: NXE:3300B overlay improvements
NXE:3300B overlay improvements Better lens performance and improved reticle clamp flatness Public Slide 30 ADT NXE:3100 NXE:3300B Measured heightmap with interferometer Translated into overlay via model Flatter reticle clamps 3nm 2nm 0.2nm Improved projection lens NCE 8nm 2.8nm 1.1nm Measured lens p
Slide 31: Full wafer dedicated chuck overlay of <1.4nm
Full wafer dedicated chuck overlay of <1.4nm Public Slide 31 Filtered S2F Chuck 1 (S2F) 8 Lot (1.3,1.3) X Y Dedicated Chuck 6 Overlay [nm] 4 1.3 1.2 1.4 1.0 1.4 1.3 2 99.7% x: 1.3 nm 0 5 nm y: 1.3 nm 1 2 3 Day
Slide 32: NXE-Immersion Matched Machine Overlay of <3.5nm
NXE-Immersion Matched Machine Overlay of <3.5nm Public Slide 32 Filtered S2F (S2F) 8 Lot (3.4,3.0) X Y 6 Matched Machine Overlay [nm] 3.5 3.2 4 2.7 3.0 2.3 3.3 2 99.7% 5 nm x: 3.4 nm y: 3.0 nm 0 1 2 3 Wafer XT:1950i reference wafers EEXY subrecipes 18par (avg field) + CPE (6 par per field)
Slide 33: Contents
Public Slide 33 Contents NXE:3100 NXE:3300B status Overview Productivity Defectivity Overlay Imaging Summary and acknowledgements
Slide 34: NXE:3300B imaging overview
NXE:3300B imaging overview Public Slide 34 • Optics • 0.33NA lens performance improvement and new off-axis illuminator • 1D • 22nm dense and isolated line-space, process window and dose reduction • 16nm line-space and process window • 2D • 24nm Contact Holes for 1x DRAM node • Logic 23nm half-pitch
Slide 35: Consistent performance of 0.33 NA lens
Consistent performance of 0.33 NA lens Wavefront error improved by a factor of 2 wrt 0.25NA lens Public Slide 35 NA 0.25 NA 0.33 NA 0.25 NA 0.33 Presentation: Martin Lowisch (Zeiss SMT AG)
Slide 36: New concept off-axis illumination to enhance process window
The NXE:3300B offers new concept off-axis illumination to enhance process window Public Slide 36 10 Exposure latitude (%) 8 6 4 2 0 0 20 40 60 80 100 120 140 Depth of focus (nm) Simulations by Tachyon SMO NXE Presentation: Martin Lowisch (Zeiss SMT AG)
Slide 37: 22nm dense and iso line-space with exposure latitude of >16%
22nm dense and iso line-space NXE:3300B with an exposure latitude of >16% Public Slide 37 Conventional illumination BE = 19.5 mJ/cm2 LWR = 3.8nm EL = 16% DoF = 130nm Conventional illumination BE = 19.5 mJ/cm2 LWR = 2.9nm EL = 19% DoF = 130nm
Slide 38: Off-axis illumination enables ~20% dose reduction
Off-axis illumination enables enhanced contrast and supports ~20% dose reduction while maintaining LWR of 3.8nm Public Slide 38 Conventional illumination BE = 19.5 mJ/cm2 LWR =3.8nm EL = 16% DoF = 130nm Quasar45 illumination BE = 15.9 mJ/cm2 LWR = 3.8nm EL = 13% DoF = 160nm Higher contrast = lower L
Slide 39: Full wafer CDU performance for 22nm dense and iso lines
Full wafer CDU performance for 22nm dense and iso lines at required performance level Public Slide 39 Dense lines H Isolated lines H FWCDU = 1.5nm FWCDU = 1.6nm Isolated lines V Dense lines V FWCDU = 1.7nm FWCDU = 1.4nm Measured with Yieldstar, targeted with SEM
Slide 40: 16nm dense lines with >15% exposure latitude
16nm dense lines with >15% exposure latitude and >120nm DoF on NXE:3300B (dipole-45 setting) Public Slide 40 16nm L/S Dipole 45X Resist A 29.0mJ/cm2 Resist B Dose = 35mJ/cm 2 Further optimization with off-axis illumination to be done -60nm -40nm -20nm 0nm +20nm +40nm +60nm +80nm
Slide 41: 24nm regular Contact Holes with Exposure Latitude >20%
24nm regular Contact Holes (DRAM 1x node) with Exposure Latitude >20%, and DOF >120nm Public Slide 41 Single exposure Conventional setting LCDU = Hole-to-hole variation over 25 CHs [nm 3σ] -80nm -60nm -40nm -20nm 0nm +20nm +40nm +60nm +80nm Resist A 26mJ/cm2 LCDU [nm 3σ] 4.0 3.6 3.2 2.9 2.8 2.9 3.2
Slide 42: NXE:3300B enables single exposure logic metal1
NXE:3300B enables single exposure logic metal1 minimum half-pitch 23 nm, conventional setting Public Slide 42
Slide 43: Metal 1 random logic, half pitch=23nm
Metal 1 random logic, half pitch=23nm illustrates sweet spot for EUV @0.33 NA Public Slide 43 focus -80nm -60nm EUV ArFi -40nm Single Exposure Double Patterning (LELE) -20nm 0nm Usable DoF Usable DoF typical ≈ Current >120nm 40..60nm 20nm 40nm 60nm 80nm
Slide 44: NXE:3300B - Good imaging performance logic metal1
NXE:3300B - Good imaging performance logic metal1 Public minimum half-pitch 23 nm, single exposure printing Slide 44
Slide 45: SRAM 2D features: 42nm Tip2Tip performance
SRAM 2D features: 42nm Tip2Tip performance Public Slide 45 Process Window of line-ends with ArFi 28nm node SRAM 90 pitch Tip2Tip CD=42nm Tip2Tip distance (CD) = 80nm Interfield CDU = 8nm EUV 10nm node SRAM 44nm pitch Tip2Tip distance (CD) = 42nm Intrafield CDU = 1.3nm
Slide 46: Resolution shown on NXE:3300B for dense line spaces and contact holes
Resolution shown on NXE:3300B for dense line spaces, regular and staggered contact holes; all single exposures Public Slide 46 14nm HP 14nm HP 18nm HP 19nm HP 13nm HP 13nm HP 17nm HP 18nm HP Dipole30, Dipole45, Quasar 30 (CAR) Large Annular (CAR) Chemically Amplified Inpria Resist Resist (CAR)
Slide 47: NXE:3300B shows single-digit (9 nm HP) patterning capability
NXE:3300B shows single-digit (9 nm HP) patterning capability! Public using spacer-assisted double patterning (SADP) Slide 47 NXE litho Core etch Spacer dep. Spacer etch (single expose, 18nm HP) 9 nm HP Demonstrated 9 nm half-pitch L/S pattern with EUV single SADP flow. Litho Conditions: - ASML NXE:3
Slide 48: Contents
Public Slide 48 Contents NXE:3100 NXE:3300B status Overview Productivity Defectivity Overlay Imaging Summary and acknowledgements
Slide 49: Summary
Summary 13nm HP Public Slide 49 • NXE:3100 in use for process and device development at customers • NXE:3300B tested and qualified, 11 systems in various 60 phases of integration 50 • Overlay performance of DCO<2nm and MMO<4nm 40 demonstrated Power [W] 30 55W EUV Power • Good imaging performance for
Slide 50: Acknowledgements
Acknowledgements Public Slide 50 The work presented today, is the result of hard work and dedication of teams at ASML and many technology partners worldwide including our customers Special thanks to our partners and customers for allowing us to use some of their data in this presentation ASML and pa