Applied Materials, Inc. · NASDAQ:AMAT
Applied Materials — Investor Day (June 2026)
78 slides from Applied Materials's investor day presentation, Jun 25, 2026
Slide 1: Powering DRAM and Advanced Packaging Inflections
MASTER CLASS June 25, 2026 Powering DRAM and Advanced Packaging Inflections with Materials Innovation and Process Control
Slide 2: Forward Looking Statements
Forward Looking Statements This presentation contains forward-looking statements, including those regarding anticipated growth and trends in our businesses and markets, industry outlooks and demand drivers, technology transitions, our business and financial performance and market share positions, ou
Slide 3: Michael Sullivan
MASTER CLASS June 25, 2026 Michael Sullivan Corporate Vice President Head of Investor Relations
Slide 4: Prior View of Semi and WFE Markets
Prior View of Semi and WFE Markets 4 | Applied Materials External
Slide 5: AI Accelerating Semiconductor Demand
AI Accelerating Semiconductor Demand WAVES OF AI-DRIVEN GROWTH PHYSICAL AI Semiconductor industry revenues can potentially reach AGENTIC AI $1T this year INFERENCING AI TRAINING AI Source: SIA, Applied Materials 5 | Applied Materials External
Slide 6: WFE Market Outlook
WFE Market Outlook MOST ENABLING TECHNOLOGIES FOR AI COMPUTING PERFORMANCE AND POWER DEVICE INFLECTIONS Leading-Edge Gate-all-around transistors Foundry/Logic Backside power delivery AP P L I E D M AT E R I AL S 4F2 Process DRAM 3D DRAM Equipment Company in All High-bandwidth memory (HBM) Three Mark
Slide 7: Agenda
Mike Sullivan AGENDA Welcome and Introduction 9:00 Kevin Moraes, Ph.D. Innovation and Technology Strategy Sony Varghese, Ph.D. 9:15 DRAM and High Bandwidth Memory (HBM) Jinho An, Ph.D. 9:30 Advanced Packaging Lior Engel 9:45 Process Control Q&A 10:00 Kevin, Sony, Jinho, Lior, Mike 7 | Applied Materi
Slide 8: Kevin Moraes, Ph.D.
MASTER CLASS June 25, 2026 Kevin Moraes, Ph.D. Corporate Vice President Strategy and Marketing Semiconductor Products Group
Slide 9: Inflection-Focused Innovation
Inflection-Focused Innovation Co-Innovate Deliver Working with Valuable new customers to products, chip deliver the most manufacturing valuable solutions processes and from a uniquely AIx services broad portfolio Share Value Create Value To increase As customers ramp margins, R&D more valuable silic
Slide 10: Broad Capabilities Delivered as Unique Connected Solutions
Broad Capabilities Delivered as Unique Connected Solutions Applied Competitors ALD ✓ ✓ ✓ ✓ UNIQUE COMBINATIONS Bonding partner ✓ Cleans partner ✓ ✓ Unit #1 CMP ✓ Process Tools #1 CVD ✓ ✓ ✓ ✓ ✓ ECD ✓ ✓ #1 Epitaxy ✓ ✓ Etch ✓ ✓ ✓ ✓ Co-optimized Solutions Furnace partner ✓ #1 Implant ✓ Lithography partn
Slide 11: Applied Materials DRAM Share Growth
Applied Materials DRAM Share Growth » Ported transistor integrated materials solutions from logic to DRAM to increase DRAM I/O speed DRAM Leadership » Gained share in DRAM EUV patterning with co-optimized Draco CVD and increased share by Sym3 etch for capacitor scaling ~10pts in 10 years » Largest s
Slide 12: DRAM Case Study
DRAM Case Study Over half a billion dollars in annual revenue 12 | Applied Materials External
Slide 13: DRAM Case Study
DRAM Case Study Over a billion dollars in annual revenue 13 | Applied Materials External
Slide 14: Advanced Packaging Case Study
Advanced Packaging Case Study #1 in HBM packaging Advanced packaging business growing >50% 14 | Applied Materials External
Slide 15: DRAM Inflections
DRAM Inflections DRAM Die Source: TechInsights 6F2 Scaling with EUV Advanced Periphery Transistors and Wiring Wiring Dielectric Planar FinFET CMOS-Bonded Array 4F2 Architecture 3D DRAM DRAM Peripheral Arrays Circuitry 15 | Applied Materials External
Slide 16: Advanced Packaging Inflections
Advanced Packaging Inflections Cold Field Emission Silicon Interposer Panel eBeam 16 | Applied Materials External
Slide 17: Basic Computing Architecture
Basic Computing Architecture xPU Main Memory I/O Devices Processor DRAM NAND SSD Data Secondary Storage ALU CU NAND, HDD Arithmetic Logic Unit Control Unit Instructions Input Output SRAM Cache Keyboard, Mouse Monitor, Printer L1 / L2 / L3 Address Space Scanner, Sensor Speaker, LED System Bus 17 | Ap
Slide 18: Ideal Memory Characteristics
Ideal Memory Characteristics Low Latency High Bandwidth Random Access Unlimited Endurance Non-Volatile Low Cost 18 | Applied Materials External
Slide 19: NAND Tradeoffs
NAND Tradeoffs NAND Characteristics Block (MBs) High Density Page Page Page Page Low Cost Page/Block Data Access Page Page Page Page Block Erase Only Page Page Page Page High Voltage Stress Page Page Page Page 19 | Applied Materials External
Slide 20: Memory Characteristics
Memory Characteristics Memory Type Access Time* Energy Use** SRAM SRAM Cache 1 second 1x High Bandwidth Memory ~10 seconds ~40x DRAM DDR DIMM ~1-2 minutes ~100x NAND SSD Tens of hours ~1,000x *Normalized access time per bit, with SRAM as baseline **Normalized read energy per bit, with SRAM as baseli
Slide 21: Basic Computing Architecture: Memory Wall
Basic Computing Architecture CPU waits idle xPU Speed Memory Latency ~5 GHz, ~0.2 ns/cycle for memory access ~50-100 ns access ~250-500x Speed Gap xPU Main Memory I/O Devices Processor DRAM NAND SSD Data Secondary Storage ALU CU NAND, HDD Arithmetic Logic Unit Control Unit Instructions Input Output
Slide 22: Memory and KV Cache Relationship
Memory and KV Cache Relationship Words Already Processed Applied Materials DRAM KV Cache Memory Usage vs. Context Length & Concurrent Users 160 160GB and Advanced Packaging KV Cache Memory (GB) Master Class 120 KV Cache 4 Users Keys Values 80 80GB 2 Users 40 40GB 1 User 0 2k 8k 32k 64k 128k Context
Slide 23: Sony Varghese, Ph.D.
MASTER CLASS June 25, 2026 Sony Varghese, Ph.D. Managing Director Technology Strategy Semiconductor Products Group
Slide 24: DRAM Primer
DRAM Primer DRAM Cell DRAM Cell Area 1T1C 8F2 6F2 4F2 bitline wordline capacitor 2F 4F 2F storage node bit line 2F 3F bitline contact contact 2F wordline transistor 24 | Applied Materials External
Slide 25: DRAM Primer
DRAM Primer DRAM Cell 1T 1C 1 capacitor bitline wordline transistor 25 | Applied Materials External
Slide 26: DRAM Primer
DRAM Primer DRAM Cell DRAM Array 1T 1C Bitline 0 1 0 0 0 0 0 1 0 1 0 0 1 1 0 1 Wordline capacitor bitline wordline Sense Amps & Peripheral Circuitry transistor Data Bus 26 | Applied Materials External
Slide 27: DRAM Inflection 1: EUV Scaling in 6F2
DRAM Inflection 1: EUV Scaling in 6F2 EUV scaling produces taller features Improving EUV line patterns Applied: #1 in DRAM conductor etch Sym3 Y Magnum Etch Mask CDU Improvement 21% Wordline >20% Polymer deposition and etch cycling Incoming Conventional Sym3 Y DRAM cell array smoothens sidewalls Etc
Slide 28: DRAM Inflection 2: Logic Technology Adoption
DRAM Inflection 2: Logic Technology Adoption Epi Interconnect Periphery Logic → FinFET Centura Prime Epi 20% Embedded footprint reduction SiGe:B High-K Metal Gate FinFET Planar FET 28 | Applied Materials External
Slide 29: DRAM Inflection 3: CMOS-Bonded Array
DRAM Inflection 3: CMOS-Bonded Array Memory Array DRAM Wafer Periphery Logic Array + Periphery Conventional DRAM CMOS-Bonded Array Array + Periphery Memory Array Wafer Periphery Logic Density and Die density 1x Die density ~1.4x Same die size as array Efficiency Cell efficiency ~60% Cell efficiency
Slide 30: DRAM Inflection 4: 4F2 Architecture
DRAM Inflection 4: 4F2 Architecture 6F2 4F2 BCAT Transistor Vertical Transistor Main Gate Shared Back Gate Gate Oxide 2F 2F BCAT: Buried Channel Array Transistor 3F 2F 30 | Applied Materials External
Slide 31: DRAM Inflection 4: Vertical Cell Transistors | Channel Etching
DRAM Inflection 4: Vertical Cell Transistors | Channel Etching Sym3 Z Magnum Etch Shallow Trench Isolation Etch 31 | Applied Materials External
Slide 32: DRAM Inflection 4: Vertical Cell Transistors | Gate Oxide
DRAM Inflection 4: Vertical Cell Transistors | Gate Oxide ALD Oxide Deposition Oxide Densification Oxide Interface Treatment Conformal Nitridation Gate Oxide Treatment Centura DPX Treatment Centura RPO2 Radiance Treatment Centura DPX Treatment 32 | Applied Materials External
Slide 33: DRAM Inflection 4: Vertical Cell Transistors | Metal Gate Stack
DRAM Inflection 4: Vertical Cell Transistors | Metal Gate Stack Endura Trillium ALD Gate Metal Deposition 33 | Applied Materials External
Slide 34: DRAM Inflection 4: Vertical Cell Transistors | Buried Metal Gate
DRAM Inflection 4: Vertical Cell Transistors | Buried Metal Gate Producer Selectra Etch Gate Recess 34 | Applied Materials External
Slide 35: DRAM Inflection 4: Vertical Cell Transistors | Bitline Junction
DRAM Inflection 4: Vertical Cell Transistors | Bitline Junction 6F2 4F2 bitline junctions Low-Temp Selective Epi System Bitline Junction bitlines 35 | Applied Materials External
Slide 36: DRAM Inflection 5: 3D DRAM
DRAM Inflection 5: 3D DRAM 6F2 4F2 3D DRAM 36 | Applied Materials External
Slide 37: DRAM Inflection 5: 3D DRAM
DRAM Inflection 5: 3D DRAM 3D NAND 3D DRAM (Channel / Bit line) Poly Si Core SiO Tunnel oxide Charge trap SiN Blocking oxide AlO TiN W or Mo (Word line) Requires alternating layers of insulating dielectric material, Relies heavily on conductor and metal stack and memory holes are formed using dielec
Slide 38: Collaborative platform for high-velocity innovation and commercialization
Collaborative platform for high-velocity innovation and commercialization of next-generation technology | Applied Materials External
Slide 39: DRAM Inflection 5: 3D DRAM | Epi Superlattice
DRAM Inflection 5: 3D DRAM | Epi Superlattice Epi Superlattice >100 Layer Mold Stack Si + SiGe Epitaxy Deep Trench Etch Deep Trench Gap Fill SiGe Selective Recess Wordline Engineering Si Lateral Selective Epi SiGe Lateral Selective Metal Applied Test Structure for 3D DRAM Tuned surface chemistry del
Slide 40: DRAM Inflection 5: 3D DRAM | High-Aspect-Ratio Etch
DRAM Inflection 5: 3D DRAM | High-Aspect-Ratio Etch Epi Superlattice High Aspect Ratio Si Etch >150:1 aspect ratio Co-optimized Deep Trench Etch Processes Deep Trench Gap Fill SiGe Selective Recess Wordline Engineering Lateral Selective Epi Lateral Selective Metal Applied Test Structure for 3D DRAM
Slide 41: DRAM Inflection 5: 3D DRAM | High-Aspect-Ratio Gap Fill
DRAM Inflection 5: 3D DRAM | High-Aspect-Ratio Gap Fill Epi Superlattice High Aspect Ratio Gap Fill >150:1 aspect ratio Co-optimized Deep Trench Etch Processes Deep Trench Gap Fill SiGe Selective Recess Wordline Engineering Lateral Selective Epi Lateral Selective Metal Applied Test Structure for 3D
Slide 42: DRAM Inflection 5: 3D DRAM | Selective Lateral Recess
DRAM Inflection 5: 3D DRAM | Selective Lateral Recess Epi Superlattice Lateral SiGe Recess >100:1 selectivity Deep Trench Etch Deep Trench Gap Fill New Process SiGe Selective Recess Technology Wordline Engineering Lateral Selective Epi Lateral Selective Metal Applied Test Structure for 3D DRAM Highl
Slide 43: DRAM Inflection 5: 3D DRAM | Wordline Engineering
DRAM Inflection 5: 3D DRAM | Wordline Engineering Epi Superlattice Wordline Engineering Deep Trench Etch Deep Trench Gap Fill SiGe Selective Recess New Process Wordline Engineering Technology Lateral Selective Epi Lateral Selective Metal Applied Test Structure for 3D DRAM Engineered metal grain grow
Slide 44: DRAM Inflection 5: 3D DRAM | Lateral Selective Epi
DRAM Inflection 5: 3D DRAM | Lateral Selective Epi Epi Superlattice Lateral Selective Epi Deep Trench Etch Deep Trench Gap Fill SiGe Selective Recess Wordline Engineering New Lateral Selective Epi Technologies Co-optimized Lateral Selective Metal Applied Test Structure for 3D DRAM Non-line-of-sight
Slide 45: DRAM Inflection 5: 3D DRAM | Lateral Selective Epi
DRAM Inflection 5: 3D DRAM | Lateral Selective Epi Epi Superlattice Lateral Metal Deposition Deep Trench Etch Deep Trench Gap Fill SiGe Selective Recess Wordline Engineering New Lateral Selective Epi Technologies Co-optimized Lateral Selective Metal Applied Test Structure for 3D DRAM Advanced therma
Slide 46: HBM: Stacked DRAM Dies
HBM: Stacked DRAM Dies DRAM chip TSV DRAM HBM HBM HBM HBM DRAM DRAM HBM HBM HBM HBM controller AI Accelerator die logic controller die HBM3: >>1024 I/O TSVs HBM Stack HBM4: >>2048 I/O TSVs DDR DRAM die: 64 I/O 46 | Applied Materials External
Slide 47: Jinho An, Ph.D.
MASTER CLASS June 25, 2026 Jinho An, Ph.D. Senior Director Heterogeneous Integration Semiconductor Products Group
Slide 48: More Than Moore
More Than Moore In 1965, Gordon Moore predicted both the exponential increase of transistors on a chip, and conditions that would drive the disaggregation of the system-on-chip. “ It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and in
Slide 49: The System-on-a-Chip (SoC) Era
The System-on-a-Chip (SoC) Era 3D model of chip Microscope cross section view of chip Stacked copper interconnects Server chip (SoC) Transistors 49 | Applied Materials External
Slide 50: The System-in-a-Package (SiP) Era
The System-in-a-Package (SiP) Era 3700 SOC Era SiP Era Server Chip (SoC) Modern AI Superchip (SiP) 3200 AMD GPU 2700 Die size (mm2) 2200 Nvidia AMD 1700 CPU Intel 1200 Reticle Limit: ~860mm2 700 200 Source: Applied Materials, Evercore ISI Research, Anandtech, wccftech.com, techpowerup.com, Locuza 50
Slide 51: SoC System Integration
SoC System Integration DRAM modules PCIe Slots Server Chip Server Chip lid DRAM modules CPU die substrate Printed Circuit Board (“Motherboard”) with Components Cross section of Server Chip 51 | Applied Materials External
Slide 52: Interposers
Interposers Chip on Wafer on Silicon Interposer Substrate with Si Enables high-density chip interconnects through fine-pitch silicon wiring and TSVs Interposer (CoWoS-S) Chip on Wafer on Epoxy Interposer with Redistribution Layer (RDL) Substrate with RDL Uses organic polymer layers for cost-effectiv
Slide 53: Advancing Advanced Packaging
Advancing Advanced Packaging 2D 2.5D side-by-side chips on PCB dies on silicon interposer 3D 3.5D vertical die 3D stacks on stacking via TSVs 2.5D interposer 53 | Applied Materials External
Slide 54: Packaging Interconnects
Packaging Interconnects 2D Package Flip-Chip Wire Bonds Solder Bumps Technique Thin wires arced from chip Round solder joints connect Defining Feature pads to substrate substrate to PCB I/O Density ~10/mm² <100/mm² Energy per Bit ~10 pJ/bit ~20 pJ/bit 54 | Applied Materials External
Slide 55: Packaging Interconnects (continued)
Packaging Interconnects (continued) Hybrid bonds TSVs CPO Microbumps Through-Silicon Vias Co-Packaged Optics Technique Microbumps Hybrid Bonds (TSVs) (CPO) Small solder joints Vertical copper vias Direct copper-to- On-package fiber-optic Defining Feature connecting chips to etched through silicon co
Slide 56: Bridging Chips to Boards: Substrates
Bridging Chips to Boards: Substrates Chips Interposer solder bumps RDL TSVs RDL Substrate PCB 56 | Applied Materials External
Slide 57: The Path to Super-sized AI Chips: Panel Interposers
The Path to Super-sized AI Chips: Panel Interposers ▪ ▪ ▪ ▪ ▪ ▪ ▪ Panel Future AI Interposers Superchip Up to 5x larger than wafer ▪ Package size: 9x Large interposer houses ▪ Silicon area: >>600x hundreds of chips ▪ # of dies: 400 ▪ 310x310mm, 510x515mm, 600x600mm ▪ Enables 14x-reticle-size interpo
Slide 58: Co-optimized Panel Manufacturing Solutions
Co-optimized Panel Manufacturing Solutions Lithography Deposition Deposition Etch Deposition eBeam (PVD) (CVD) (ECD) Metrology Applied leveraging its front-end process technologies and display expertise for panel packaging Maskless digital Topaz for panels up Topaz for panels up Advanced patterning
Slide 59: High-Bandwidth Memory: Incremental Materials Engineering Steps
High-Bandwidth Memory: Incremental Materials Engineering Steps DRAM Wafer TSV Formation TSV Etch CVD Liner PVD Barrier-Seed Cu Plating CMP Front side Bump Bond Pad Formation PVD Plating Resist Strip Under-Bump Etch (frontside) > 700 steps DRAM nodes, e.g. 1A, 1B, 1C. Steps common for standard and HB
Slide 60: Enabling Thinner DRAM for HBM4 and Beyond
Enabling Thinner DRAM for HBM4 and Beyond Stress-Engineered Backside TSV Films SiN liner bow- TEOS layer compensation layer Si Cu Oxide substrate TSV liner Carrier wafer Producer Avila 2 PECVD 60 | Applied Materials External
Slide 61: Hybrid Bonding Flow
Hybrid Bonding Flow Producer CVD Sym3 Etch Endura PVD Nokota ECD Opta CMP Sym3 Etch Kinex Integrated D2W Hybrid Bonder Dielectric Stack Damascene RDL/Pad Barrier / Seed PVD Copper Pad Fill CMP with Tuned Wafer Singulation Surface Preparation Hybrid Bonding CVD Formation Etch ECD Dishing Control Prod
Slide 62: Lowering Hybrid Bonding Queue Time to Increase Yield
Lowering Hybrid Bonding Queue Time to Increase Yield Stand-Alone Solution Kinex Surface Preparation Surface Preparation 13hrs** 1hr*** Higher queue time Lower queue time Gap Fused Contamination risk Improved adhesion Improved yield Kinex Integrated Die-to-Wafer Hybrid Bonding System 62 | Applied Mat
Slide 63: Advanced Packaging CMP Innovations
Advanced Packaging CMP Innovations Chemical Mechanical Planarization (CMP) Opta Quad CMP Copper Fill with TSV thickness variation TSV Oxide Dielectric High wafer-within-wafer Low wafer-within-wafer total total thickness variation with thickness variation conventional CMP Oxide Dielectric with thickn
Slide 64: Advanced Packaging ECD Innovations
Advanced Packaging ECD Innovations Cu Pad TSV Fill Nokota Vmax 2 ECD Conventional ECD Nokota enables void- struggles to deliver and defect-free TSV chemistry in high-aspect- fill for dimensions as ratio structures, resulting small as 3 microns void in voids and defects TSV Barrier / Seed PVD µbump a
Slide 65: Advanced Packaging Enables Co-Packaged Optics
Advanced Packaging Enables Co-Packaged Optics Electronic Integrated Laser Mod. Circuit (EIC) fibers driver driver coupler hybrid bonds connectors Photonic Integrated Laser Modulator Electrical-to-Optical Circuit (PIC) µbumps E/O Transmission Waveguide Si bridge TSVs Interposer Co-Packaged Optics (CP
Slide 66: More Than Moore
More Than Moore In 1965, Gordon Moore predicted both the exponential increase of transistors on a chip, and conditions that would drive the disaggregation of the system-on-chip. “ It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and in
Slide 67: Lior Engel
MASTER CLASS June 25, 2026 Lior Engel Corporate Vice President Imaging and Process Control Group
Slide 68: Advanced Packaging Needs Advanced Process Control
Advanced Packaging Needs Advanced Process Control Traditional Packaging Served by Optical Emerging Advanced Packaging Needs Particle on bump Small particles are becoming yield killers Solder bumps >20um <10um <8um measurements Micro-bumps Microbumps Hybrid Bonds Physical probers Bump damage Cu pad d
Slide 69: eBeam Benefits in Advanced Packaging
eBeam Benefits in Advanced Packaging Non-Contact Higher Resolution Tilted / 3D Imaging Material Identification Electrical Test Top Tilted Optical eBeam Organic residue on glass wafer Cross Cross Detector section section C O e e Sidewall Si e e Count Top View Tilted View Energy Level 69 | Applied Mat
Slide 70: eBeam Leadership
eBeam Leadership 1980s Today eBeam Innovation Begins #1 Market Position 40+ Years of eBeam Leadership 70 | Applied Materials External
Slide 71: eBeam Enabling Process Control in Advanced Packaging
eBeam Enabling Process Control in Advanced Packaging High-Density 3D Architectures Diverse Substrates and Warpage Challenges HBM Various Thicknesses Standard ~0.7mm ~2mm Stacked GPU/SRAM Various Materials Warped Through-Silicon Vias 71 | Applied Materials External
Slide 72: CD Metrology – VeritySEM 7AP
CD Metrology – VeritySEM 7AP Metrology Wafer Handling Capability Hybrid Bonding Pads Varied 0.7mm Diameter, barrier seed roughness 0.7mm-1.6mm Thicknesses 1.6mm TSV Top/Bottom CD, slant, sidewall Warpage Unique tilted beam capability Microbump Fully Automated Diameter, height, cross-wafer trends Too
Slide 73: Optical Inspection and Defect Review Flow
Optical Inspection and Defect Review Flow Gap fill crack Organic residue light eBeam Cu damage Probe scratch column lens electron Upper beam Limit ~60° ~0.5° Lower Bin A Bin B Bin C Bin D Limit Optical Inspection Defect Map eBeam Defect Review Defect Binning Control Chart SEMVision G7AP Defect Analy
Slide 74: Kevin Moraes, Ph.D.
MASTER CLASS June 25, 2026 Kevin Moraes, Ph.D. Corporate Vice President Strategy and Marketing Semiconductor Products Group
Slide 75: Exceeding Previous Growth Expectations
Exceeding Previous Growth Expectations Growing by Enabling Leadership in Periphery Well Positioned for Growth the Capacitor Roadmap Transistor and Interconnect in Advanced Packaging Scaling >3x >4x >$2B >50% growth >$2B $2B ~$1.7B >$1B ~$1.4B $1B ~$0.5B 2020-24 2020-24 Next 5 2020-24 2020-24 Next 5
Slide 76: EPIC Center Gaining Momentum
EPIC CENTER GAINING MOMENTUM F O U N D I N G PA R T N E R S I N N O VAT I O N PA R T N E R S R E S E A R C H PA R T N E R S Micron Samsung Advantest SCREEN ASU RPI SK hynix TSMC Broadcom Stanford 76 | Applied Materials External
Slide 77: Key Takeaways
Key Takeaways Demand is accelerating and Leading-edge foundry-logic (F/L), DRAM, and advanced packaging are most critical to broadening with incremental AI enabling improvements in tokens per second per watt and are driving the vast majority of drivers WFE investment growth. Applied’s DRAM leadershi
Slide 78: Applied Materials
APPLIED — MATERIALS.. ~ Material Innovation