Analog Devices, Inc. · NASDAQ:ADI
Analog Devices — Technical Presentation (February 2014)
45 slides from Analog Devices's technical presentation, February 2014
Slide 1: SHARC Processor Overview
The World Leader in High Performance Signal Processing Solutions SHARC Processor Overview David Miller SHARC Applications Engineering Manager
Slide 2: Agenda
Agenda • Target Markets • SHARC Processor advantages • Family Summary • SHARC Hardware Overview • I/O Processor • Direct Memory Access • SHARC Peripherals • Additional Support • Resources
Slide 3: Analog Devices SHARC Processor Family
Analog Devices SHARC Processor Family
Slide 4: SHARC: Floating-Point Processor
SHARC: Floating-Point Processor Performance Partners Operating High Integration 2.4 GFLOPS Temperature RAM, SPORTs, Ambient: SRC, UARTs 105oC Wide range of floating-point processors from $5 to $25 Close collaboration with partners High integration enables single-chip solutions
Slide 5: Target Markets
Target Markets Digital Home Pro-Audio Established leadership market Established leadership market position in digital home position in pro-audio • Advanced TVs • Mixers • High definition DVD • Amplifiers • Home theater systems • Synthesizers Industrial Automotive and Instrumentation Established lead
Slide 6: SHARC Features
SHARC Features • High performance 32-bit/40-bit floating-point operations • High performance 32-bit fixed-point operations • Up to 400 MHz (2.5 ns) core instruction rate • Performs 2400 MFLOPS/800 MMACS • Single-Instruction Multiple-Data (SIMD) computational architecture provides: • Two computationa
Slide 7: Common and Market-Specific Advantages of SHARC Features
Common and Market-Specific Advantages of SHARC Features • 32-bit floating-point Common • Large on-chip memory Advantages • Glueless I/F to external memory • Audio decoders in ROM Special • Sample rate converters (HW) Advantages in Consumer • S/PDIF Rx/Tx (HW) and Automotive Automotive- • DTCP cipher
Slide 8: Floating-Point Product Portfolio
Floating-Point Product Portfolio Performance/Integration ADSP-21161 ADSP-21262/21266 ADSP-21362–21366 ADSP-21367–21369 • 0.6 GFLOPS • 1.2 GFLOPS • 2 GFLOPS • 2.4 GFLOPS • Audio processing acceleration • Optimized for system and performance cost Low Cost ADSP-21065L ADSP-21261 ADSP-21371/21375 • 0.37
Slide 9: SHARC Family Summary
SHARC Family Summary Key Features ADSP- ADSP- ADSP- ADSP- ADSP- ADSP- ADSP- ADSP- ADSP- ADSP- ADSP- ADSP- ADSP- ADSP- 21161 21261 21262 21266 21362 21363 21364 21365 21366 21367 21368 21369 21371 21375 RAM/ROM (Mbits) 0/1 1/3 2/4 2/4 3/4 3/4 3/4 3/4 3/4 2/6 2/6 2/6 1/4 0.5/2 Max Frequency 110 150 20
Slide 10: Pin-Compatibility
Pin-Compatibility Low-pin-count devices with SRAM interface Features ADSP‐21261 ADSP‐21262 ADSP‐21364 ADSP‐21366 Pipeline stages 3 3 5 5 Frequency – MHz (max) 150 200 333 333 Audio Decoders in ROM No No No Yes On‐Chip RAM – Mbits 1 2 3 3 Serial Ports 6 6 6 6 External Memory Interface SRAM, Flash SRA
Slide 11: Pin-Compatibility
Pin-Compatibility With SDRAM support Key Features ADSP-21367 ADSP-21369 ADSP-21375 ADSP-21371 Max Frequency MHz 400 400 266 266 RAM – Mbits 2 2 0.5 1 SDRAM Clk MHz 166 166 133 133 SDRAM Bus Width 32 32 16 32 UART Yes Yes Yes Yes TWI Yes Yes Yes Yes Serial Ports 8 8 4 8 Audio Decoders in ROM Yes No N
Slide 12: SHARC Hardware Overview
SHARC Hardware Overview ANALOG DEVICES
Slide 13: ADSP-21369 Architecture Block Diagram
ADSP-21369 Architecture Block Diagram
Slide 14: SHARC SIMD Core
SHARC SIMD Core CACHE MEMORY DAG 1 DAG 2 PROGRAM 8 x 4 x 32 8 x 4 x 32 SEQUENCER PMA BUS 32 PMA DMA BUS 32 DMA PMD BUS 64 PMD BUS CONNECT DMD BUS 64 DMD Processing Element X Processing Element Y REGISTER REGISTER FILE MULTIPLIER/ FILE BARREL MULTIPLIER/ BARREL ALU MAC ALU SHIFTER MAC SHIFTER
Slide 15: ADSP-21369 Architecture Block Diagram
ADSP-21369 Architecture Block Diagram
Slide 16: Integrated RAM and ROM
Integrated RAM and ROM • On-chip RAM • Same speed as core Product RAM (Mbits) ROM (Mbits) • Zero wait states for code/data access ADSP-21362 3 4 • Improves performance over external memory ADSP-21363 3 4 • Predictable performance ADSP-21364 3 4 • RAM blocks are partitioned to allow ADSP-21365 3 4 si
Slide 17: External Memory Interface in SHARCs
External Memory Interface in SHARCs Product SDRAM SRAM Parallel Flash ADSP-21362–21366 3 3 ADSP-21367–21369 3 3 3 ADSP-21375 3 3 3 ADSP-21371 3 3 3 • SHARC processors allow glueless connection to external memory • SDRAMs • Supports SDRAMs of 64 Mbits, 128 Mbits, 256 Mbits, and 512 Mbits with configu
Slide 18: Enhanced SHARC Instruction Cache
Enhanced SHARC Instruction Cache (ADSP-21371 and ADSP-21375) Instruction Cache 32-Bit x 48-Bit Program Sequencer External Port SDRAM Data PM Address Bus Controller Packing DM Address Bus Control Unit Asynchronous PM Data Bus Memory Address DM Data Bus Interface • 32-entry two-way set associative cac
Slide 19: I/O Processor
1/O Processor ANALOG DEVICES
Slide 20: ADSP-21369 Architecture Block Diagram
ADSP-21369 Architecture Block Diagram
Slide 21: I/O Processor Features
I/O Processor Features • The I/O processor supports I/O for the SHARC • Communicates between external world and the SHARC’s core and on-chip memory • DMA controller with up to 34 DMA channels • 16 for SPORTs, four for UARTs, two for SPIs, two for external ports, two for memory to memory, eight for i
Slide 22: Advantages of SRU/DAI/DPI
Advantages of SRU/DAI/DPI • Most designs leave pins: • Unused • Connected in parallel • Tied low • Tied high • More pins = more die area = higher cost • Why pay for a pin if you are just going to tie it to ground? • As on-chip peripherals increase there is less need to route their I/O off-chip (more
Slide 23: Direct Memory Access (DMA)
Direct Memory Access (DMA) ANALOG DEVICES
Slide 24: ADSP-21369 Architecture Block Diagram
ADSP-21369 Architecture Block Diagram
Slide 25: Direct Memory Access (DMA)
Direct Memory Access (DMA) • Allows for zero-overhead background transfers at full clock rate without processor intervention • Both code and data can be transferred through DMA • DMA transfers occur at 532 Mbytes/s* • Relieves the core processor from the task of moving data from peripherals to inter
Slide 26: DMA Features
DMA Features • DMA transfers are configured and initiated by the SHARC core processor • 34 DMA channels on ADSP-2136x, 32 DMA channels on ADSP-2137x • DMA can be paused and restarted; different peripherals support different flavors of DMA, such as circular buffering, chaining, etc. • DMA can compete
Slide 27: SHARC Peripherals
SHARC Peripherals ANALOG DEVICES
Slide 28: ADSP-21369 Architecture Block Diagram
ADSP-21369 Architecture Block Diagram
Slide 29: SHARC Synchronous Serial Ports (SPORTs)
SHARC Synchronous Serial Ports (SPORTs) • Designed to be an extremely flexible serial interface to the SHARC processor • Supports interfacing to several types of serial devices and SHARC to SHARC communications • Supports interfacing to devices with a 3- to 32-bit serial word length • SPORTs have se
Slide 30: SHARC SPORTs
SHARC SPORTs • Operates up to 1/8 of the processor core clock • Supports full duplex • Each SPORT has four signals • SCLK, frame sync, data A, data B • Each can be independently configured for one of four modes • Normal SPORT mode • Multichannel TDM mode (128 channels per frame) • I2S mode (24 I2S c
Slide 31: SPORTs Configuration
SPORTs Configuration • Signal routing unit allows for multiple SPORTs to be arbitrarily combined to run off as little as one SCLK and frame sync source • SPORTs can be configured for a number of different input and output options • Data signals are configured through software as inputs or outputs •
Slide 32: Industry Standard Serial Interfaces
Industry Standard Serial Interfaces • Serial Peripheral Interface (SPI) • 4-wire serial interface (developed by Motorola) that enables the SHARC processor to communicate with other SPI-compatible devices • The SPI port features • Full duplex operation, Master and slave mode, Multimaster mode, Open d
Slide 33: Sample Rate Converters
Sample Rate Converters • 4 independent asynchronous stereo sample rate converters (SRC). • Each converter supports • The SRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources • Provides up to 128
Slide 34: Precision Clock Generators
Precision Clock Generators • 4 independent Precision Clock Generators (PCG) • Each PCG generates a clock and frame sync signal • The PCG’s output can be routed to on chip peripherals or off chip via the SRU
Slide 35: Timers and PWM module
Timers and PWM module • Up to 4 timers • One core timer • 3 General Purpose timers • Core timer • Counts core clock cycles and generates an interrupt when count expires • 3 General Purpose Timers • Counts at the IOP clock rate • Independent of one another • Generate periodic interrupts • Pulse wavef
Slide 36: ADSP-21369 Architecture Block Diagram
ADSP-21369 Architecture Block Diagram
Slide 37: Development Tools
Development Tools ANALOG DEVICES
Slide 38: CROSSCORE development tools product line
CROSSCORE®, Analog Devices development tools product line, provides easier and more robust methods for engineers to develop and optimize systems by shortening product development cycles for faster time to market. CROSSCORE includes: • VisualDSP++® integrated development and debugging environment • E
Slide 39: VisualDSP++ Features
VisualDSP++ Features • Connectionless IDDE • Session Wizard • Automatic Breakpoints • Code Generation Tools • C/C++ Compiler, C/C++ Run-Time Library, DSP & Math Libraries, Assembler, Linker, Loader & Splitter • Compiled Simulation • Compiler Annotations • Profile Guided Optimization • VisualDSP++ RT
Slide 40: Hardware
Hardware EZ-KIT Lite • EZ-KIT Lite provides developers with an easy EZ-KIT Lite and cost-effective method for initial evaluation • ADSP-21375 EZ-KIT Lite of an ADI processor or DSP • ADSP-21369 EZ-KIT Lite • Includes a DSP desktop evaluation board and • ADSP-21364 EZ-KIT Lite evaluation version of V
Slide 41: Additional Support: Third Parties and Software
Additional Support Third Parties and Software
Slide 42: SHARC Third Parties
SHARC Third Parties • AeVee Labs is a full-service electronics engineering firm specializing in audio, video, telecommunications, digital signal processing, and more. We provide the expertise to produce advanced, reliable products and a reputation for high performance that can improve market accepta
Slide 43: Extensive Audio Algorithm Library
Extensive Audio Algorithm Library • Licensed Algorithms: • Dolby® • ADI library algorithms: • AC3, DPL2x, EX, DVS, DH • Post-processing algorithms • Filters (EQ, tone control, cross-over) • Loudness • Dynamics processing • Audistry (in design) • Delay-management • Mixers/clickless volume control • D
Slide 44: Conclusion
Conclusion • Target Markets – SHARC is suited to a variety of applications • SHARC Processor advantages – peripherals, memory and performance • Family Summary – Large set of family members • SHARC Hardware Overview – SIMD architecture with dual comp units • I/O Processor – SRU, DAI, DPI • Direct Mem
Slide 45: For More Information
For More Information • Analog Devices website which has links to white papers, application notes, manuals, data sheets, FAQs, Knowledge Base, sample code, development tools and much more: www.analog.com/SHARC • Take a 90-day Test Drive of VisualDSP++ for SHARC processors: www.analog.com/testdrive •
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