Keysight Technologies Inc. · NYSE:KEYS
Keysight Technologies — Technical Presentation (July 2007)
48 slides from Keysight Technologies's technical presentation, Jul 24, 2007
Slide 1: Presentation on Characterization of a WLAN Transceiver
Agilent EEsof EDA Presentation on Characterization of a WLAN Transceiver This document is owned by Agilent Technologies, but is no longer kept current and may contain obsolete or inaccurate references. We regret any inconvenience this may cause. For the latest information on Agilent’s line of EEsof
Slide 2: Characterization of a WLAN Transceiver
Increased Insight with Increased Agilent EEsof EDA Characterization of a WLAN Transceiver Andy Howard Applications Engineer July 24, 2007 Group/Presentation Title Page 1 July 24, 2007 1
Slide 3: Objectives
Objectives • Show how GoldenGate makes block-level design easier • Show that GoldenGate is able to handle much more than individual blocks • Show GoldenGate’s capacity, that enables extracted view and statistical simulations you might have considered impossible • Show GoldenGate’s ability to simulat
Slide 4: Outline
Outline Block-level design flow Applying GoldenGate in block-level design of LNA, mixer, oscillator, amplifier, etc. Post-layout simulations, with and without Monte Carlo System-level simulations – combining blocks together Sinusoidal inputs, effect of blockers, modulated signals – Where does degrad
Slide 5: Block-level design flow
Block-level design flow Specs for each block from system designer (but may be “dumbed down” due to limitations of some simulators) Create layout, Run parameter sweeps, Meet YES extract parasitics, try different topologies specs? re-simulate NO NO NO YES NO Meet Run statistical YES Meet specs? simula
Slide 6: Implications for the simulator
Implications for the simulator • Simulations that yield specifications directly should be easy to setup and run • Displaying results to enable design trade-offs should be easy • Large simulation capacity necessary to handle extracted views and Monte Carlo quickly Group/Presentation Title Page 5 July
Slide 7: WLAN transceiver block diagram
WLAN transceiver block diagram Typical block level specifications: gain, gain compression, noise figure, tuning range, phase noise, output power, IP3, power consumption, blocker attenuation, sensitivity to temperature, frequency response, noise levels, etc. System level specifications: EVM, ACPR, BE
Slide 8: LNA design - determining optimal source impedance for minimum noise figure
LNA design - determining optimal source impedance for minimum noise figure Group/Presentation Title Page 7 July 24, 2007 Most of the simulations shown are for characterizing blocks that are complete or nearly complete. This setup is for simulating a portion of the LNA (low-noise amplifier) to determ
Slide 9: LNA simulations
LNA simulations Part of LNA subcircuit, with DC back-annotation Group/Presentation Title Page 8 July 24, 2007 This shows a simulation setup for the LNA. The subcircuit shows the back- annotation of DC voltages to the schematic. 8
Slide 10: LNA S-parameters and noise
LNA S-parameters and noise Device noise contribution listing output Turning on device noise contribution listing output Group/Presentation Title Page 9 July 24, 2007 If you have never seen GoldenGate before, it is an alternative simulator within the Cadence Analog Design Environment window. There ar
Slide 11: Noise figure and gain versus frequency
Noise figure and gain versus frequency Group/Presentation Title Page 10 July 24, 2007 This shows the GoldenGate tool qWave displaying S21 and the noise figure. The Cadence tools such as Wavescan could be used for displaying these results, or since GoldenGate will now write ADS or RFDE dataset files,
Slide 12: 1-dB power gain compression setup
1-dB power gain compression setup GC is a harmonic balance analysis specifically for computing power gain compression Specify input source and output probe Specify amount of compression in dB Specify input power range Group/Presentation Title Page 11 July 24, 2007 Gain compression is another importa
Slide 13: Computing results
Computing results These functions are specific to the GC analysis Return output power at 1-dB gain compression, Gain in linear region, Input power at gain compression point Results output automatically when simulation finishes Group/Presentation Title Page 12 July 24, 2007 GoldenGate knows the type
Slide 14: Plot showing gain compression
Plot showing gain compression Group/Presentation Title Page 13 July 24, 2007 This plot shows the gain compression and what the output power would be if there where no gain compression. 13
Slide 15: If you want voltage gain and gain compression
If you want voltage gain and gain compression Use CR analysis and sweep input power, “pin” Both power and voltage gain may be computed Group/Presentation Title Page 14 July 24, 2007 If you want voltage gain compression, use “CR” analysis and a sweep of the input power. Here voltage gain is defined a
Slide 16: Simulation results
Simulation results Power and voltage gains both output Voltage gain compression may be computed in Data Display Group/Presentation Title Page 15 July 24, 2007 This shows the simulation results output to the log file and the voltage gain compression at the output plotted versus the available source p
Slide 17: Mixer noise figure
Mixer noise figure This scheme is OK if no DC bias is needed RF In Baseband Out analogLib ideal_balun LO voltage source LO DC bias Group/Presentation Title Page 16 July 24, 2007 This shows a setup for simulating the mixer noise figure and conversion gain. This setup will be OK if there is no need to
Slide 18: Mixer noise figure simulation setup
Mixer noise figure simulation setup SSNA is a harmonic balance analysis specifically for noise Specify LO tone Specify small- signal input tone Specify output probe and output signal indices Specify noise figure type It would be difficult to set this up incorrectly! Group/Presentation Title Page 17
Slide 19: Mixer noise figure simulation results
Mixer noise figure simulation results Various gains, noise figure, and other noise data are output by the simulator automatically. Group/Presentation Title Page 18 July 24, 2007 Various gains and noise voltages are output by the simulator automatically without requiring you to write equations. “nois
Slide 20: Noise figure and conversion gain versus LO amplitude
Noise figure and conversion gain versus LO amplitude Sweeping 14 values of LO Can sweep other amplitude required 13 seconds. parameters easily Group/Presentation Title Page 19 July 24, 2007 This qWave plot shows the noise figure and conversion gain versus the LO amplitude. Clearly if this amplitude
Slide 21: Mixer IP3
Mixer IP3 IP is a harmonic balance analysis specifically for computing intercept points Specify: circuit type, IP Rank, power or voltage, input and LO (if a mixer) frequencies, source and output probe It would be difficult to set Fast IPN works only with IP Rank 3 this up incorrectly! Group/Presenta
Slide 22: Mixer IP3 outputs
Mixer IP3 outputs Linear extrapolation of IP3 point Group/Presentation Title Page 21 July 24, 2007 This shows the graphically-extracted output IP3 point. 21
Slide 23: Mixer conversion gain compression
Mixer conversion gain compression Use CR analysis for voltage conversion gain compression, GC for power conversion gain compression Group/Presentation Title Page 22 July 24, 2007 This simulation is for determining voltage conversion gain compression. The input- and output-referred IP3 points are com
Slide 24: VCO simulation
VCO simulation Common RFIC oscillator topology Varactor diodes S-parameters from Momentum simulation of spiral Group/Presentation Title Page 23 July 24, 2007 We will analyze the voltage-controlled oscillator next. This simulation uses S-parameter data, which was generated by a Momentum (a 3-D planar
Slide 25: Checking for instability
Checking for instability Eigenvalue Computation is preferred, but Nyquist must be used if circuit contains S-parameter model(s) A single unstable frequency is found, as expected May run stability analysis on non-oscillator circuits, also. Group/Presentation Title Page 24 July 24, 2007 An initial osc
Slide 26: Steady-state behavior versus tuning voltage
Steady-state behavior versus tuning voltage Run CR analysis with Oscillator Analysis specified. Varactor tuning voltage swept. Fosc is the approximate frequency of oscillation. Tuning sensitivity computed with diff() Group/Presentation Title Page 25 July 24, 2007 Oscillator analysis is carried out a
Slide 27: Compute phase noise
Compute phase noise Noise contribution table data output for each offset frequency Group/Presentation Title Page 26 July 24, 2007 This shows phase noise simulation results as well as a noise contribution listing at the 100 kHz offset frequency. Flicker noise from several PMOS devices at the core of
Slide 28: Simulating LNA and mixer together
Simulating LNA and mixer together Noise figure, IP3, gain, and gain compression Small-signal noise analysis results LO source uses NoiseCor to re-use spectrum and noise from VCO and prescaler simulation Group/Presentation Title Page 27 July 24, 2007 Now we will simulate the LNA and mixer together be
Slide 29: Simulating IP3 of LNA and mixer
Simulating IP3 of LNA and mixer Uses same schematic. Uses CR analysis to compute voltage IP3 points Simulation run at two input power levels to verify slopes of fundamental and intermod tones Group/Presentation Title Page 28 July 24, 2007 This IP3 simulation uses CR analysis and several performances
Slide 30: IP3 simulation results
IP3 simulation results These slopes are correct (1dB/dB and 3dB/dB) so graphical extrapolation of IP3 point is valid Group/Presentation Title Page 29 July 24, 2007 This shows the desired fundamental tone at the output as well as the undesired intermodulation distortion term. The slopes are correct.
Slide 31: Gain compression
Gain compression Run previous simulation, sweeping input power high enough to cause gain compression Group/Presentation Title Page 30 July 24, 2007 Voltage gain compression may be simulated from the same setup, just sweeping the input power high enough to cause gain compression. The IP3 points may b
Slide 32: Conversion gain and noise figure of extracted view, with Monte Carlo
Conversion gain and noise figure of extracted view, with Monte Carlo 100 Monte Carlo trials required about 31 minutes (single CPU) 50,870 netlist elements, 371 Mbytes total memory required Group/Presentation Title Page 31 July 24, 2007 The simulations up until now have been of schematic views. Now w
Slide 33: Correlation data
Correlation data Indicates which process statistical variables have the biggest effect on circuit performances Group/Presentation Title Page 32 July 24, 2007 The upper right tables show (in order) the correlations between the statistical variables and the two performances, voltage gain and noise fig
Slide 34: Output IP3 and conversion gain of extracted view, with Monte Carlo
Output IP3 and conversion gain of extracted view, with Monte Carlo 100 Monte Carlo trials required about 115 minutes (single CPU) Group/Presentation Title Page 33 July 24, 2007 This shows the IP3 and conversion gain statistical results. The conversion gain distribution is about the same. The variati
Slide 35: Receiver, LNA, mixers, frequency divider, analog baseband chains, extracted view
Receiver, LNA, 2 mixers, frequency divider, 2 analog baseband chains, extracted view Noise figure and small-signal conversion gain 100 Monte Carlo iterations required 6.5 hours w/LSF (could be reduced with all CPUs=fastest in cluster.) Small-signal 64,931 netlist elements, source 1475 nonlinear mode
Slide 36: Receiver, LNA, mixers, frequency divider, analog baseband chains, extracted view
Receiver, LNA, 2 mixers, frequency divider, 2 analog baseband chains, extracted view WLAN input signal, requires 51 minutes and 54 seconds for 8192 time points. 408 Mbytes total memory. WLAN Source, 64,934 netlist elements, reads I and Q data 1475 nonlinear models LNA LO source, re-uses VCO Frequenc
Slide 37: Transmitter compression simulation
Transmitter compression simulation Q Baseband In RF 1 MHz sines Out Freq Div Power Amp Balun LO at 2.611 GHz I Baseband In Group/Presentation Title Page 36 July 24, 2007 Up to this point we have run simulations of the receiver. We could re-run similar simulations on the blocks in the transmitter, bu
Slide 38: Simulation results
Simulation results Output {1,1} LO tone BB tone index index LO {1,0} Phase of Q input set 90 degrees behind phase of I input Required ~21 minutes for sweep Group/Presentation Title Page 37 July 24, 2007 The spectrum shows the desired signal at the LO + baseband frequency. Undesired distortion terms
Slide 39: Double-sideband simulation results
Double-sideband simulation results Q and I inputs in phase Compression occurs earlier Group/Presentation Title Page 38 July 24, 2007 This shows the results of the same simulation, except with the I- and Q- baseband input signals in phase, which produces a double-sideband output spectrum. A compariso
Slide 40: With WLAN baseband input signals
With WLAN baseband input signals ScaleFact scales amplitude of I and Q baseband input signals Required about 91 minutes Group/Presentation Title Page 39 July 24, 2007 This shows simulation results with baseband WLAN I and Q input signals. These signals came from a Ptolemy simulation. The Ptolemy Tim
Slide 41: EVM at different points
EVM at different points PA Output Mixer Outputs BB Chain Outputs Group/Presentation Title Page 40 July 24, 2007 This shows the EVM at different points in the transmitter, as a function of the scale factor. The biggest EVM occurs at the output of the PA, although the mixer does contribute some distor
Slide 42: Trajectory diagrams at power amplifier output
Trajectory diagrams at power amplifier output Group/Presentation Title Page 41 July 24, 2007 This shows the trajectory diagrams at the output of the power amplifier for the lowest and highest values of the scale factor. The right plot clearly shows compression relative to the left one. 41
Slide 43: Extracted view simulation with WLAN signals
Extracted view simulation with WLAN signals ScaleFact scales amplitude of I and Q baseband input signals Extracted view simulation required about 8 hours Group/Presentation Title Page 42 July 24, 2007 The previous two simulations were of schematic views. This simulation uses extracted views of the a
Slide 44: Several additional capabilities
Several additional capabilities • Parallelism to speed up Monte Carlo (and other) simulations • Job Manager Group/Presentation Title Page 43 July 24, 2007 There are several capabilities GoldenGate offers that I wanted to emphasize. One is the use of multiple computers in parallel, that speeds up Mon
Slide 45: Job Manager examples
Job Manager examples Enables multiple simulations to be run from same ADE session Harmonic “calibration” Corner analysis Various analyses in parallel (if multiple CPUs available) Group/Presentation Title Page 44 July 24, 2007 The Job Manager enables you to run multiple simulations from the same ADE
Slide 46: Additional examples from customers using GoldenGate
Additional examples from customers using GoldenGate • Harmonic Balance Capacity – Receiver for Video Application 20K active devices, 20K passive – Noise figure analysis with SSNA (127 harmonics) < 12 hours • Fast Envelope – 2800 Active devices, 3200 Passive elements, QAM 256 Source – ACPR produced w
Slide 47: Conclusion
Conclusion GoldenGate is “tuned” for easy block-level design and simulation GoldenGate has the capacity to simulate large extracted views and multiple blocks together GoldenGate’s Monte Carlo simulation capabilities (especially with parallelism) move statistical design from a step you skip to someth
Slide 48: For more information about Agilent
For more information about Agilent Email Updates www.agilent.com Agilent EEsof EDA, visit: www.agilent.com/find/emailupdates For more information on Agilent Technologies’ products, applications or services, please Get the latest information on the www.agilent.com/find/eesof products and applications y
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