Vicor Corporation · NASDAQ:VICR
Vicor — Technical Presentation (2019)
47 slides from Vicor's technical presentation, Nov 20, 2019
Slide 1: PCB Layout and Thermal Design Techniques for High Density Power Systems
PCB Layout and Thermal Design Techniques for High Density Power Systems Author: Joseph Aguilar Presenter: Paul Yeaman, Senior Director, Applications Engineering ©2019 Vicor 1
Slide 2: Outline
Outline Background Thermal Design Considerations PDN Overview High-Current Routing Layout Parasitic Considerations Examples Conclusion ©2019 Vicor 2
Slide 3: Background
Background PCB Layout is critical for removing heat and delivering power in a system Designers often overlook the PCB, resulting in poor designs and inadequate performance This workshop will cover important aspects of PCB design to maximize heat transfer and minimize power delivery impedance a
Slide 4: Thermal – Overview
Thermal – Overview Two primary heat transfer paths Heat sink / Coldplate PCB ©2019 Vicor 4
Slide 5: Thermal – Heat Transfer
Thermal – Heat Transfer Convection Conduction Transfer of heat through forced air (or other liquid) Transfer of heat by direct contact ©2019 Vicor 5
Slide 6: Thermal – Resistance
Model heat transfer as equivalent electrical circuit: Power Dissipation = Current Source Thermal – Resistance Thermal impedance = Resistor Temperature boundaries = Voltage Source In air cooled systems, heat conducted to the heat sink and PCB must transfer to the ambient air through convection.
Slide 7: Thermal – Resistance
Thermal – Resistance 0.6 C/W ϴINT_-OUT_TOP 0.9 C/W 1.7 C/W 2.0 C/W 12 C/W ϴINT_-OUT_BOT ϴINT_-OUT_PINS ϴINT_+OUT_PINS ϴINT_SIG Complex Thermal Model: T-OUT_TOP T-OUT_BOT T-OUT_PINS T+OUT_PINS TSIG Separate thermal impedance for each net/PCB land Identify lowest-resistance path – maximize Cu on PCB ©
Slide 8: Thermal Vias
Thermal Vias FR4 ineffective for heat transfer (insulator) Top Side Only Thermal Vias conduct heat to opposite side of board Increase effective surface for convection cooling Top and Bottom ©2019 Vicor 8
Slide 9: PCB Via Types
Blind Via: Start on outer PCB Via Types layer, end on inner layer Blind/Buried vias = Higher density, added cost/complexity/lead time TH via = Lower density, reduced cost/complexity/lead time Buried Via: Start and end on inner layer Through-hole Via: Standard hole drilled through PCB from top to bot
Slide 10: Via In Pad Plated Over (VIPPO)
VIPPO vs. Traditional Via In Pad Plated Over (VIPPO) Traditional Via Capped and Plated Via VIPPO: Traditional: Direct transfer into PCB Increased parasitics Advantages of VIPPO Drawbacks Epoxy Fill • High density, fine pitch fan out (i.e., BGA) • Higher Cost/Lead time • Lower inductance • 8-10 steps
Slide 11: Thermal Example1 – TH Via
Thermal Example1 – TH Via LGA Regulator + External Inductor Through-Hole Vias (no VIPPO) VOUT LGA Land Pattern PGND VIN LGA Regulator Thermal Model VIN, PGND, VOUT = lowest thermal impedance: Thermal vias and extended Cu ©2019 Vicor 11
Slide 12: Thermal Example – TH Vias
Thermal Example 1 – TH Vias Top View of SIP Bottom View Extended Cu and thermal vias on Top layer VOU increase surface area for T convection VOUT Thermal vias between pads PGND PGN Conduct heat to D bottom layer Additional Cu on bottom layer for VIN VI critical nets N ©2019 Vicor 12
Slide 13: Thermal Example 2 – Via in Pad
Thermal Example 2 – Via in Pad High-current driver module(MCD) Via in pad Blind/Buried Vias MCD Package MCD Thermal Model PGND = Primary cooling path: Thermal vias and extended Cu ©2019 Vicor 13
Slide 14: Thermal – Circuit Simulation
Thermal – Circuit Simulation Construct the thermal model from device data sheet Apply power dissipation as current source Define thermal boundary Voltage sources – ambient, case, PCB etc. ©2019 Vicor 14
Slide 15: Thermal Circuit Simulation Example
Thermal Circuit Simulation Example Example: • 54VIN, 500A, PDISS = 24W • Internal Temperature Limit: 100°C Sweep TCASE and TPCB 50 – 100°C Results: Use results to determine temperature limits • For TCASE of 85°C, Max TPCB = 65°C for thermal design • For TPCB = 90°C, Max TCASE = 50°C ©2019 Vicor 15
Slide 16: Thermal – Summary
Thermal – Summary Maximize copper on critical nets – Use multiple layers – Copper on outer layers is most effective – Extend past part – First inner layer should have copper planes for thermal mass on critical nets Use Thermal Vias to conduct heat to additional layers – Opposite side of PCB – Cl
Slide 17: Power Delivery Network (PDN)
Power Delivery Network (PDN) High-Current Module ©2019 Vicor 17
Slide 18: PDN
PDN Decoupling Socket Bypass Distribution to Sense Point VR Output Stage Caps Socket Caps+vias Pins Power delivery network between Voltage Regulator and CPU Includes power planes, capacitors, vias and socket ©2019 Vicor 18
Slide 19: Output Impedance
Output Impedance High di/dt load step response dominated by open-loop output impedance of converter and PDN ΔV = ΔI*ZOUT ZOUT Open-Loop output impedance ZOUT_CL = ZOUT above Crossover ZOUT_CL = ZOUT / T inside of closed-loop BW (equals open-loop impedance) (open-loop impedance reduced by loop gain)
Slide 20: PDN Effect on Load Transient
PDN Effect on Load Transient PDN impedance excluding VR Key frequency range for load step PDN impedance vs. Frequency ©2019 Vicor 20
Slide 21: PDN Effect on Load Transient
PDN Effect on Load Transient 1000A/µs 50 – 550A load Step 500A/µs 250A/µs Assuming ‘perfect’ VR with ZOUT = 0Ω, 500A transient (500A/µs) results in ~120mV deviation in VOUT due to socket and PCB Faster Slew rate results in higher frequency excitation ©2019 Vicor 21
Slide 22: PDN Effect on Load Transient
PDN Effect on Load Transient Total Response at VSENSE Open loop – Excludes VR Separating Effects of PCB L and R RDIST between Regulator and LDIST Socket Total ©2019 Vicor 22
Slide 23: PCB Layout Considerations
PCB Layout Considerations Power Planes – Resistance and Inductance of planes – Power dissipation in PCB – Via resistance and placement Capacitors – Capacitor Placement – ESR,ESL,FSR – Via placement and loop inductance Board Stackup – Number of dedicated Power/GND layers – Copper weight – Diele
Slide 24: Board Stackup and Floorplan
Board Stackup and Floorplan Critical to define up front – Overall layer count and definition Number of power/ground layers Dedicated signal routing layers – Board and dielectric thickness Nets and layers impedance controlled routing or special considerations ©2019 Vicor 24
Slide 25: Board Stackup – 14-Layer Example
Controlled Impedance Parasitic Inductance Limit Board Stackup – 14-Layer Example Parasitic Capacitance Limit Load ©2019 Vicor 25
Slide 26: Power Plane Resistance – Squares method
Power Plane Resistance – Squares method For a square of Copper W = L Resistance is independent of size R = Total resistance A = Cross-sectional area of plane W = Width T = Thickness, defined by copper weight Ρ = Resistivity of Copper, typically 1.7µΩ-cm (0.67µΩ-in) at 25°C Copper Weight oz Thickness
Slide 27: Power Plane Inductance – Rule of Thumb
Power Plane Inductance – Rule of Thumb = Inductance per square of two adjacent parallel power planes approximately 32pH per mil of dielectric Example: 3.1mil dielectric approximately 100pH per square* *Eric Bogatin EDN Rule of thumb #16 September 2014 ©2019 Vicor 27
Slide 28: Via Resistance
Via Resistance Current Flow Cross-sectional area Resistance of Via equivalent to resistance of trace with equivalent CSA and length Plating Thickness Material µΩ-cm µΩ-in Hole Diameter Copper 1.70 0.67 Copper (plated) 6.0 2.36 Gold 2.2 0.87 *Note: resistivity of plated copper can be higher than pure
Slide 29: Via example
Current Via example Via Details: 6mil drill, 1mil copper plating 68mils length 0.67µΩ-in (cu) resistivity = ©2019 Vicor 29
Slide 30: Via Inductance
Via Inductance Where: Lvia = inductance of via, nH D = via diameter, in. H = length of via, in. *Johnson and Graham, High-Speed Digital Design - page 259 ©2019 Vicor 30
Slide 31: Conductor Current – Carrying Capacity
Conductor Current – Carrying Capacity Use IPC guidelines on current-carrying capacity IPC-2221A and IPC-2152 Temperature rise vs. current and cross section Conservative curves apply to internal and external conductors Example: 100mil trace, 2oz copper, 30°C temperature rise @ 12A IPC2221A –
Slide 32: Via Current-Carrying Capacity
Via Current-Carrying Capacity From IPC-2152 page 26: – The cross-sectional area of a via should have at least the same cross- sectional area as the conductor or be larger than the conductor coming into it. If the via has less cross-sectional area than the conductor, then multiple vias can be used
Slide 33: Parasitic Capacitance
Parasitic Capacitance Where: H = distance between planes (cm) A = area of common planes (cm2) εr = dielectric Permeability (4.5 for FR-4) Lower dielectric spacing will decrease inductance but increase capacitance Source: High Speed Analog Design and Application Seminar: http://www.ti.com/lit/ml/slyp
Slide 34: Decoupling Capacitor Selection
Decoupling Capacitor Selection Considerations: Low ESR critical for filtering high- 0402 frequency switching currents 1206 Capacitor equivalent circuit model Ineffective for filtering beyond FSR – Review FSR, ESL against signal frequency ESR Smaller caps generally more effective for higher- Se
Slide 35: Small Ceramic Capacitor MLCC & LICC
Small Ceramic Capacitor MLCC & LICC 1> Datas heet: 3> Simulation: CMLCC CLICC IN 0.9µ 0.9µ AC 1 0 RMLCC RLICC V1 9m 8.5m LMLCC LLICC 0.9n 160p .ac dec 511 100k 1G V(in)/I(Rmlcc) V(in)/I(Rlicc) 10 100° 60° 1 20° 0.1 -20° 0.01 -60° 0.001 -100° 100KHz 1MHz 10MHz 100MHz 1GHz ©2019 Vicor 35
Slide 36: Via loop inductance
Via loop inductance Inductance increases with loop area ©2019 Vicor 36
Slide 37: Decoupling Capacitance Placement
Decoupling Capacitance Placement Worse Place bypass capacitors as close to device pins Via placement and capacitor pad as possible. spacing matters! Use planes to connect Minimize via separation. Place vias close to Better pads or use VIPPO Use smaller caps (0402) for high-frequency bypassing
Slide 38: High-Current Example
High-Current Example High-current module HC PDN Socket Decoupling/ Load(Bottom) LOAD HC PDN Bypass Caps 0.8V 650A TDC 1200A Peak Bottom (Load) View 1048 pins 1mm pitch BGA Top View ©2019 Vicor 38
Slide 39: High-Current Example
High-Current Example For high-current designs it’s critical to use large planes and maximize the number of layers dedicated to power/return 2oz copper used on inner layers 14-Layer PCB VDD and VSS layers interleaved to minimize Inductance ©2019 Vicor 39
Slide 40: High-Current Example – Vias
High-Current Example – Vias L2 L1(Top) 6mil L1-L2 Vias in pad 6x per terminal T 11x per GND Pad O 8mil L2-L13 Vias P 18mil L2-L13 Vias Vias stacked on L2 L2-L13 6mil L14-L13 Vias in pad B 1x per BGA O T 18mil L13-L2 stacked T O Caps directly opposite M 1 per BGA pair L2 and L1 overlay L14(Bot) 6mil
Slide 41: Decoupling Example
Decoupling Example Load transient 1,000A at 10,000A/µs Caps in socket above CH1 Vout: 100mV/div Timebase: 200nsec/div CPU to decouple load CH2: Iout: 300A/div from PDN Caps at device output attenuate ripple Via in pad 0402 caps placed across pins 3.0MHz effective ripple frequency ©2019 Vicor 41
Slide 42: High-Current Example: Transient Response
High-Current Example: Transient Response CH1 Vout: 100mV/div Timebase: 200nsec/div CH2: Iout: 300A/div CH1 Vout: 100mV/div Timebase: 5usec/div CH2: Iout: 300A/div 100 to 1100A transient @ ~10,000A/µs ~160mV undershoot ©2019 Vicor 42
Slide 43: Parasitic Capacitance Example
Parasitic Capacitance Example High-current VSW (15A RMS) module driver High-current modules (x4) Switch Nodes VS1/VS2: • Differential output: one driver to four modules • Trapezoidal Voltage: ~50VP-P (differential) • Sinusoidal current: ~15A RMS • Parasitic Capacitance Limit: 140pF Max VS1-VS2 capac
Slide 44: Parasitic Capacitance – VS1/VS2
Parasitic Capacitance – VS1/VS2 Total VS1-VS2 Capacitance limited (140pF) VS1 VS1/VS2 Stackup CVS1_GND CVS1_VS2 VSS A = 0.55in2 = 3.54838cm2 CVS1-VS2 = 78pF CVS2_GND VS2 CVS1-GND = CVS2-GND = 91pF Equivalent Circuit CTOTAL = = 123.5pF VS1/VS2 overlaid on adjacent layers ©2019 Vicor 44
Slide 45: Example Low-Inductance Routing – GA/GB
Example Low-Inductance Routing – GA/GB Large plane – minimize squares Gate Drive GateA/GateB One driver to four modules Routed between adjacent ground planes 5V, 1.5MHz (tRISE<100ns) (Minimize inductance) Parasitic Inductance Limit: 1nH Stackup ©2019 Vicor 45
Slide 46: Conclusion
Conclusion As demonstrated, high-density PCB layout can be very challenging due to varying requirements of devices and signals A good stackup and floor plan is a critical foundation for a good layout Layout must be considered as part of the electrical and thermal design and incorporated into s
Slide 47: Thank you
Thank you Questions? The information contained herein and presented by Vicor is for general informational purposes only. Vicor assumes no responsibility for inaccuracies, errors or omissions in this presentation. Users of power supply products remain responsible for the design, testing and operation