Formfactor, Inc. · NASDAQ:FORM
Formfactor — Technical Presentation (June 2011)
14 slides from Formfactor's technical presentation, Jun 12, 2011
Slide 1: Key Design Parameters to Maximize Probe Current Carrying Capability
June 12 to 15, 2011 San Diego, CA Key Design Parameters to Maximize Probe Current Carrying Capability January Kister MicroProbe
Slide 2: Overview
Overview • Key System-on-a-Chip (SoC) Semiconductor Trends Influencing Probe Current Carrying Capability (CCC) • Definition of CCC • Variables Affecting CCC • Trade-offs Between CCC, Probe Deflection Range, and Inductance • Example of Optimized Solution • Summary June 12 to 15, 2011 IEEE SW Test Wor
Slide 3: Key Semiconductor Trends Influencing CCC
Key Semiconductor Trends Influencing CCC • Geometries Are Getting Smaller – Logic/SoC full-grid-array pitches continue to shrink from today’s 130µm to sub-100µm by 2016 (ITRS roadmap) – Thru-silicon-via (TSV) technology will require sub-50um pitch in full-grid arrays before 2013 • Current Densities
Slide 4: Definition of CCC
Definition of CCC • CCC = Current which results in a 20% contact force reduction – Below plot typical of SEMI-defined methodology • CCC modulated by several variables – Here, improvement achieved through probe material conductivity (electrical and thermal) and high temperature strength increase June
Slide 5: Variable 1: Probe Material Properties
Variable 1: Probe Material Properties 1. Bulk resistivity – Lower resistivity lowers temperature rise from Joule (I2R) heating 2. Yield and fatigue strength (at elevated temperature) – High mechanical strength at elevated temperatures better supports probe deflection stress at operating conditions 3
Slide 6: Variable 2: Probe Geometry
Variable 2: Probe Geometry • Probe Cross Section (pitch) – A BIG EFFECT! – Slender probes (ie, probes at smaller pitch) have reduced CCC because of: • Higher stress • Higher electrical resistance • Lower convective heat transfer • Probe Length – Shorter probes offer higher CCC because of shorter dis
Slide 7: Variable 3: Probe Layout
Variable 3: Probe Layout • Example: – Single isolated probe measures 1.05Amp CCC at room temperature – Add a neighbor 130µm away, CCC drops to 0.95Amp – Add another neighbor 130µm away, CCC drops to 0.91Amp • In a 3x3 matrix at 130µm pitch, center probe CCC is 0.89Amp – 15% reduction in CCC from iso
Slide 8: Variable 4: Chuck/Wafer Temperature
Variable 4: Chuck/Wafer Temperature • Example: 1.9Amp CCC @ 25C degrades to 0.9Amp CCC @ 180C – Higher temperature inhibits heat transfer from probe – Reduced heat transfer = Decreased Probe CCC • CCC as a function of wafer temperature • Data for 75µm probe deflection June 12 to 15, 2011 IEEE SW Tes
Slide 9: Variable 5: Probe Tip Contact Resistance
Variable 5: Probe Tip Contact Resistance • Example: 1.3Amp @ 3Ω Cres drops to 1.12Amp @ 10Ω Cres – Tip-to-pad resistance increases local heat generation through I2R losses and decreases local thermal conductivity through material property changes – Increased heat generation & reduced heat transfer =
Slide 10: Variable 6: Electrical Duty Cycle
Variable 6: Electrical Duty Cycle • Typical probes reach steady-state temperature in under 2sec • For shorter current-ON intervals should consider equivalent DC current and from there the required CCC value June 12 to 15, 2011 IEEE SW Test Workshop 10
Slide 11: Variable 7: Dynamic Cycling
Variable 7: Dynamic Cycling • Example: 1.8Amp CCC reduced to 1.4Amp if 10k Cycles required – Determines not only what current level a probe can carry one time, but also how many cycles a probe can sustain at various current levels below the static CCC Example of dynamic CCC test result correlating c
Slide 12: The Trade-Off: CCC, Deflection, and Inductance
The Trade-Off: CCC, Deflection, and Inductance Short Probe Long/Slender Probe • High CCC • Large deflection range Advantages • Small Self-Inductance (able to absorb large (high frequency) bump co-planarity) • Small deflection range • Low CCC Disadvantages (unable to absorb large • Large Self-Inducta
Slide 13: Example of Optimized Solution
Example of Optimized Solution • Dual-probe design with composite (multi-material) probe structure – Independent optimization of power, ground, and I/O probes – Satisfy multiple requirements, while “deconstraining” from a single-probe design June 12 to 15, 2011 IEEE SW Test Workshop 13
Slide 14: Summary
Summary • Production-worthy SoC probe cards must satisfy competing mechanical and electrical requirements – Current Carrying Capacity (CCC) becoming increasingly challenging as pitches shrink • Requirements can be mutually exclusive with a single-probe, single-material design – 1Amp/probe in sub-100