Synopsys, Inc. · NASDAQ:SNPS
Synopsys — Technical Presentation (October 2002)
17 slides from Synopsys's technical presentation, Oct 8, 2002
Slide 1: Behavioural Model of a DCDC Converter written in VHDL-AMS
Behavioural Model of a DCDC Converter written in VHDL-AMS SYNOPSYS User Group Saber (SNUG Saber), October,8th,2002,Munich Behavioural Model of a DCDC Converter written in VHDL-AMS Ewald Hessel, Lippstadt 1
Slide 2: Contents
Contents 1.) Introduction: Behavioural Models / VDL-AMS 2.) DCDC Converter: Specification Realization 3.) Model Description: Graphical Structure Behavioural Models 4.) Simulation Results 5.) Conclusion SYNOPSYS User Group Saber (SNUG Saber), October,8th,2002,Munich Behavioural Model of a DCDC Conver
Slide 3: Introduction: Behavioural Models / VHDL-AMS
1.) Introduction : Behavioural Models / VHDL-AMS Types of Models: - physical models -> design, analysis, optimization of details - behavioural or experimental model-> system analysis VHDL-AMS: - toolindependent standard -> IEEE 1076.1 - different labels of modeling -> structure, behaviour (equations
Slide 4: DCDC Converter: Specification (Main Points)
2.) DCDC Converter : Specification ( Main Points) Future cars : 2 voltages for board net: 42V, 14V -> DCDC Converter for both directions Buck Mode 42 V 14 V Boost Mode 42 V 14 V - input voltage 30V ... 50V - input voltage 9V ... 16V - output voltage 14V (12V ...16V) - output voltage 42V (36V ...48V)
Slide 5: DCDC Converter: Specification (realization)
2) DCDC Converter : Specification ( realization) Physical Structure very complex structure with heterogeneous parts : uC,power,analog,digital,HF => - different methods for design and simulation - different tools SYNOPSYS User Group Saber (SNUG Saber), October,8th,2002,Munich Behavioural Model of a D
Slide 6: Model Description: System in Buck Mode (42V 14V)
3.) Model Description :System in Buck Mode (42V 14V) u42 u14 dcdc_ua14 double switch buck mode double switch u14 u42 switch switch u14_ref u42 u14 dcdc_ua42 boost mode u42_ref u14_ref u42_ref up_down on_off SYNOPSYS User Group Saber (SNUG Saber), October,8th,2002,Munich Behavioural Model of a DCDC C
Slide 7: Model Description: Graphical Structure of Behavioural Model
3.) Model Description : Graphical Structure of Behavioural Model SYNOPSYS User Group Saber (SNUG Saber), October,8th,2002,Munich Behavioural Model of a DCDC Converter written in VHDL-AMS Ewald Hessel, Lippstadt 7
Slide 8: Model Description: Model of a Switch (VHDL-AMS)
3.) Model Description : Model of a Switch (VHDL-AMS) ARCHITECTURE ideal OF switch IS QUANTITY v ACROSS i THROUGH p TO m; BEGIN IF ctrl USE v == 0.0; -- switch closed ELSE i == 0.0; -- switch open END USE; BREAK ON ctrl; END architecture ideal; library ieee; use ieee.math_real.all; USE work.energy_sy
Slide 9: Model Description: Graphical Structure of Behavioural Model
3.) Model Description : Graphical Structure of Behavioural Model SYNOPSYS User Group Saber (SNUG Saber), October,8th,2002,Munich Behavioural Model of a DCDC Converter written in VHDL-AMS Ewald Hessel, Lippstadt 9
Slide 10: Model Description: Converter for Buck Mode (logical structure)
3.) Model Description: Converter for Buck Mode (logical structure) resistor with dynamical input voltage: current limitation part 30 < u42 < 50 ? dynamical load r14 D i14 i42 L,R v14 v14_ref v14_0 v42 (delay) i42 = f( v42, i14, v14, efficiency ) efficiency = f( i14 ) --> table / polynom. function SY
Slide 11: Converter for Buck Mode (VHDL-AMS) [1]
3.) Model Description: Converter for Buck Mode (VHDL-AMS) [1] vr14 vd vl v14_ v14 0 Library IEEE; electrical_ref use ieee.math_real.all; ARCHITECTURE simple OF dcdc_ua14 IS USE work.electrical_systems.ALL; TERMINAL u14_0,u14_1,u14_2 : ELECTRICAL; ENTITY dcdc_ua14 IS QUANTITY v42 ACROSS i42 THROUGH u
Slide 12: Converter for Buck Mode (VHDL-AMS) [2]
3.) Model Description: Converter for Buck Mode (VHDL-AMS) [2] vr14 vd vl v14_ v14 0 electrical_ref BEGIN efficiency == 88.07 + 1.4319*ir14 - 104.28625e-3*ir14**2.0 IF ir14 <= imax_14 USE vr14 == (ud / imax_14 ) * ir14; + 3.788357e-3*ir14**3.0 - 73.44230e-6*ir14**4.0 + 719.9188e-9*ir14**5.0 -2.80269e
Slide 13: Simulation Results (current limitation)
4.) Simulation Results (current limitation) SYNOPSYS User Group Saber (SNUG Saber), October,8th,2002,Munich Behavioural Model of a DCDC Converter written in VHDL-AMS Ewald Hessel, Lippstadt 13
Slide 14: Simulation Results (switched load)
4.) Simulation Results (switched load) SYNOPSYS User Group Saber (SNUG Saber), October,8th,2002,Munich Behavioural Model of a DCDC Converter written in VHDL-AMS Ewald Hessel, Lippstadt 14
Slide 15: Conclusion: Behavioural Modeling
5.) Conclusion : Behavioural Modeling [1] Benefits: - simple model structure (independent of physical structure) - black box modeling possible - small models compared to physical models (better performance) - easy use in upper system shells - use of one universal simulation language for heterogeneou
Slide 16: Conclusion: VHDL-AMS
5.) Conclusion : VHDL-AMS [2] Benefits - toolindependent language (IEEE 1076.1) - different tools available - different modeling levels for same entity - multiple use of models - simple model exchange - standardized (public) model libraries possible Problems - only a few tools available today - actu
Slide 17: Conclusion: Growing Complexity Will Require Behavioural Modeling
5.) Conclusion [3] Growing Complexity of Future Systems Will Require Behavioural Modeling and Use of Standard Modeling Language VHDL-AMS SYNOPSYS User Group Saber (SNUG Saber), October,8th,2002,Munich Behavioural Model of a DCDC Converter written in VHDL-AMS Ewald Hessel, Lippstadt 17